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september 2009 doc id 15274 rev 4 1/95 1 stm32f105xxstm32f107xx connectivity line, arm-based 32-bit mcu with 64/256 kb flash, usb otg, ethernet, 10 timers, 2 cans, 2 adcs, 14 communication interfaces features core: arm 32-bit cortex?-m3 cpu ? 72 mhz maximum frequency, 1.25 dmips/mhz (dhrystone 2.1) performance at 0 wait state memory access ? single-cycle multiplication and hardware division memories ? 64 to 256 kbytes of flash memory ? up to 64 kbytes of general-purpose sram clock, reset and supply management ? 2.0 to 3.6 v application supply and i/os ? por, pdr, and programmable voltage detector (pvd) ? 3-to-25 mhz crystal oscillator ? internal 8 mhz factory-trimmed rc ? internal 40 khz rc with calibration ? 32 khz oscillator for rtc with calibration low power ? sleep, stop and standby modes ?v bat supply for rtc and backup registers 2 12-bit, 1 s a/d converters (16 channels) ? conversion range: 0 to 3.6 v ? sample and hold capability ? temperature sensor ? up to 2 msps in interleaved mode 2 12-bit d/a converters dma: 12-channel dma controller ? supported peripherals: timers, adcs, dac, i 2 ss, spis, i 2 cs and usarts debug mode ? serial wire debug (swd) & jtag interfaces ? cortex-m3 embedded trace macrocell? up to 80 fast i/o ports ? 51/80 i/os, all mappable on 16 external interrupt vectors and almost all 5 v-tolerant crc calculation unit, 96-bit unique id up to 10 timers with pinout remap capability ? up to four 16-bit timers, each with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? 1 16-bit motor control pwm timer with dead-time generation and emergency stop ? 2 watchdog timers (independent and window) ? systick timer: a 24-bit downcounter ? 2 16-bit basic timers to drive the dac up to 14 communication interfaces with pinout remap capability ? up to 2 i 2 c interfaces (smbus/pmbus) ? up to 5 usarts (iso 7816 interface, lin, irda capability, modem control) ? up to 3 spis (18 mbit/s), 2 with a multiplexed i 2 s interface that offers audio class accuracy via advanced pll schemes ? 2 can interfaces (2.0b active) with 512 bytes of dedicated sram ? usb 2.0 full-speed device/host/otg controller with on-chip phy that supports hnp/srp/id with 1.25 kbytes of dedicated sram ? 10/100 ethernet mac with dedicated dma and sram (4 kbytes): ieee1588 hardware support, mii/rmii available on all packages table 1. device summary reference part number stm32f105xx stm32f105r8, stm32f105v8 stm32f105rb, stm32f105vb stm32f105rc, stm32f105vc stm32f107xx stm32f107rb, stm32f107vb stm32f107rc, stm32f107vc lqfp100 14 14 mm lqfp64 10 10 mm www.st.com
contents stm32f105xx, stm32f107xx 2/95 doc id 15274 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 arm? cortex?-m3 core with embedded flash and sram . . . . . . . . . 13 2.3.2 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.3 crc (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13 2.3.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.5 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 13 2.3.6 external interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.7 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.8 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.9 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.10 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.11 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.12 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.13 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.14 rtc (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 2.3.15 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.16 i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 universal synchronous/asynchronous receiver transmitters (usarts) 18 2.3.18 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.19 inter-integrated sound (i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.20 ethernet mac interface with dedicated dma and ieee 1588 support . 19 2.3.21 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 universal serial bus on-the-go full-speed (usb otg fs) . . . . . . . . . . . 20 2.3.23 gpios (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.24 remap capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.25 adcs (analog-to-digital converters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.26 dac (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.27 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.28 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 22
stm32f105xx, stm32f107xx contents doc id 15274 rev 4 3/95 2.3.29 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.3.2 operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35 5.3.3 embedded reset and power control block characteristics . . . . . . . . . . . 35 5.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.3.7 internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.8 pll, pll2 and pll3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3.11 absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 52 5.3.12 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3.13 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.14 tim timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.15 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.16 12-bit adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 5.3.17 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 5.3.18 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
contents stm32f105xx, stm32f107xx 4/95 doc id 15274 rev 4 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 80 7 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 appendix a applicative block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 a.1 usb otg fs interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 a.2 ethernet interface solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 a.3 complete audio player solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 a.4 usb otg fs interface + ethernet/i 2 s interface solutions . . . . . . . . . . . . 89 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
stm32f105xx, stm32f107xx list of tables doc id 15274 rev 4 5/95 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f105xx and stm32f107xx features and peripheral counts . . . . . . . . . . . . . . . . . . 10 table 3. stm32f105xx and stm32f107xx family versus stm32f103xx family . . . . . . . . . . . . . . 11 table 4. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 11. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 table 13. maximum current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. maximum current consumption in run mode, code with data processing running from ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 15. maximum current consumption in sleep mode, code running from flash or ram. . . . . . . 38 table 16. typical and maximum current consumptions in stop and standby modes . . . . . . . . . . . . 3 8 table 17. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 18. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 19. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 20. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 21. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 22. hse 3-25 mhz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 table 23. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 24. hsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 25. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 26. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 27. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 28. pll2 and pll3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 29. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 30. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 31. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 32. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 33. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 34. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 35. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 36. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 37. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 38. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 39. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 40. i 2 c characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 41. scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 42. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 43. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 44. usb otg fs startup time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
list of tables stm32f105xx, stm32f107xx 6/95 doc id 15274 rev 4 table 45. usb otg fs dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 table 46. usb otg fs electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 table 47. ethernet dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 48. dynamics characteristics: ethernet mac signals for smi. . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 49. dynamics characteristics: ethernet mac signals for rmii . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 50. dynamics characteristics: ethernet mac signals for mii . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 51. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 52. r ain max for f adc = 14 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 53. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 54. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 55. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 56. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 57. lqpf100 ? 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . 77 table 58. lqfp64 ? 64 pin low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . . . . . 78 table 59. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 60. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 61. pll configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 62. applicative current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 63. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
stm32f105xx, stm32f107xx list of figures doc id 15274 rev 4 7/95 list of figures figure 1. stm32f105xx and stm32f107xx connectivity line block diagram . . . . . . . . . . . . . . . . . 12 figure 2. stm32f105xxx and stm32f107xxx connectivity line lqfp100 pinout . . . . . . . . . . . . . . 23 figure 3. stm32f105xxx and stm32f107xxx connectivity line lqfp64 pinout . . . . . . . . . . . . . . . 24 figure 4. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 8. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. typical current consumption on v bat with rtc on vs. temperature at different v bat values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 10. typical current consumption in stop mode with regulator in run mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11. typical current consumption in stop mode with regulator in low-power mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 12. typical current consumption in standby mode versus temperature at different v dd values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 13. high-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 14. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 15. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 16. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 17. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 18. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 19. i 2 c bus ac waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 20. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 21. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 22. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 23. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 24. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 25. usb otg fs timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . 65 figure 26. ethernet smi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 27. ethernet rmii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 28. ethernet mii timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 29. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 30. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 31. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 72 figure 32. power supply and reference decoupling (v ref+ connected to v dda ). . . . . . . . . . . . . . . . . 72 figure 33. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 34. lqfp100, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 35. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 36. lqfp64 ? 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 37. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 38. lqfp100 p d max vs. t a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 39. usb otg fs device mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 40. host connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 41. otg connection (any protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 42. mii mode using a 25 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 43. rmii with a 50 mhz oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 44. rmii with a 25 mhz crystal and phy with pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
list of figures stm32f105xx, stm32f107xx 8/95 doc id 15274 rev 4 figure 45. rmii with a 25 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 46. complete audio player solution 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 47. complete audio player solution 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 48. usb otg fs + ethernet solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 49. usb otg fs + i 2 s (audio) solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
stm32f105xx, stm32f107xx introduction doc id 15274 rev 4 9/95 1 introduction this datasheet provides the description of the stm32f105xx and stm32f107xx connectivity line microcontrollers. for more details on the whole stmicroelectronics stm32f10xxx family, please refer to section 2.2: full compatib ility throughout the family . the stm32f105xx and stm32f107xx datasheet should be read in conjunction with the stm32f10xxx reference manual. for information on programming, erasing and protection of the internal flash memory please refer to the stm32f10xxx flash programming manual. the reference and flash programming manuals are both available from the stmicroelectronics website www.st.com. for information on the cortex?-m3 core please refer to the cortex?-m3 technical reference manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 description the stm32f105xx and stm32f107xx connectivity line family incorporates the high- performance arm ? cortex?-m3 32-bit risc core operating at a 72 mhz frequency, high- speed embedded memories (flash memory up to 256 kbytes and sram up to 64 kbytes), and an extensive range of en hanced i/os and peri pherals connected to two apb buses. all devices offer two 12-bit adcs, four general-pur pose 16-bit timers plus a pwm timer, as well as standard and advanced communication interfaces: up to two i 2 cs, three spis, two i2ss, five usarts, an usb otg fs and two cans. ethernet is available on the stm32f107xx only. the stm32f105xx and stm32f107xx connectivity line family operates in the ?40 to +105 c temperature range, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f105xx and stm32f107xx connectivity line family offers devices in two different package types: from 64 pins to 100 pins. depe nding on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.
description stm32f105xx, stm32f107xx 10/95 doc id 15274 rev 4 these features make the stm32f105xx and stm32f107xx connectivity line microcontroller family suitable for a wide range of applications: motor drive and application control medical and handheld equipment industrial applications: plc, inverters, printers, and scanners alarm systems, video intercom, and hvac home audio equipment figure 1 shows the general block diagram of the device family. 2.1 device overview table 2. stm32f105xx and stm32f107xx features and peripheral counts peripherals (1) stm32f105rx stm32f107rx s tm32f105vx stm32f107vx flash memory in kbytes 64 128 256 128 256 64 128 256 128 256 sram in kbytes 20 32 64 48 64 20 32 64 48 64 ethernet no yes no yes timers general-purpose 4 advanced-control 1 basic 2 communication interfaces spi(i 2 s) (2) 3(2) 3(2) 3(2) 3(2) i 2 c2 1 2 1 usart 5 usb otg fs yes can 2 gpios 51 80 12-bit adc number of channels 2 16 12-bit dac number of channels 22 cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperatures ambient temperatures: ?40 to +85 c /?40 to +105 c junction temperature: ?40 to + 125 c package lqfp64 lqfp100 1. please refer to table 5: pin definitions for peripheral availability when the i/o pins are shar ed by the peripherals required by the application. 2. the spi2 and spi3 interfaces give the flexibilit y to work in either the spi mode or the i 2 s audio mode.
stm32f105xx, stm32f107xx description doc id 15274 rev 4 11/95 2.2 full compatibility throughout the family the stm32f105xx and stm32f107xx constitu te the connectivity line family whose members are fully pin-to-pin, software and feature compatible. the stm32f105xx and stm32f107xx are a drop-in replacement for the low-density (stm32f103x4/6), medium-density (stm32f103x8/b) and high-density (stm32f103xc/d/e) performance line devices, allowing the user to try different memory densities and peripherals providing a greater degree of freedom during the development cycle. table 3. stm32f105xx and stm32f107xx family versus stm32f103xx family (1) stm32 device low-density stm32f103xx devices medium-density stm32f103xx devices high-density stm32f103xx devices stm32f105xx stm32f107xx flash size (kb) 16 32 32 64 128 256 384 512 64 128 256 128 256 ram size (kb) 61 01 0 2 0 2 0 4 8 6 4 6 4 2 0 3 2 6 4 4 8 6 4 144 pins 5 usarts 4 16-bit timers, 2 basic timers, 3 spis, 2 i 2 ss, 2 i2cs, usb, can, 2 pwm timers 3 adcs, 2 dacs, 1 sdio, fsmc (100- and 144-pin packages (2) ) 100 pins 3 usarts 3 16-bit timers 2 spis, 2 i 2 cs, usb, can, 1 pwm timer 2 adcs 5 usarts, 4 16-bit timers, 2 basic timers, 3 spis, 2 i 2 ss, 2 i2cs, usb otg fs, 2 cans, 1 pwm timer, 2 adcs, 2 dacs 5 usarts, 4 16-bit timers, 2 basic timers, 3 spis, 2 i 2 s, 1 i2c, usb otg fs, 2 cans, 1 pwm timer, 2 adcs, 2 dacs, ethernet 64 pins 2 usarts 2 16-bit timers 1 spi, 1 i 2 c, usb, can, 1 pwm timer 2 adcs 2 usarts 2 16-bit timers 1 spi, 1 i 2 c, usb, can, 1 pwm timer 2 adcs 48 pins 36 pins 1. please refer to table 5: pin definitions for peripheral availability when the i/o pins are shar ed by the peripherals required by the application. 2. ports f and g are not available in devices delivered in 100-pin packages.
description stm32f105xx, stm32f107xx 12/95 doc id 15274 rev 4 2.3 overview figure 1. stm32f105xx and stm32f107xx connectivity line block diagram 1. t a = ?40 c to +85 c (suffix 6, see table 60 ) or ?40 c to +105 c (suffix 7, see table 60 ), junction temperature up to 105 c or 125 c, respectively. 2. af = alternate function on i/o port pin. pa[ 15:0] ext.it wwdg 12 b it adc1 16 adc12_in s common toadc1 & adc2 jtdi jtck/ s wclk jtm s / s wdio njtr s t jtdo nr s t v dd = 2 to 3 .6 v 8 0 af pb[ 15:0] pc[15:0] ahb toapb2 can1_rx as af 2x( 8 x16 b it) wkup gpio port a p gpio port b p f m a x : 72 mhz v ss s cl, s da, s mba i2c2 (1) gp dma1 tim2 tim 3 xt al o s c 3 -25 mhz xtal 3 2khz o s c_in o s c_out c_o o s c 3 2_out o s c 3 2_in apb1 : f m a x = 3 6 mhz hclk as af fl as h 256 kb volt a ge reg. 3 . 3 v to 1. 8 v v dd1 8 power b a ck u p interf a ce as af tim4 b us m a tri x 64 b it interf a ce rtc rc h s cortex-m 3 cpu i bus d bus o b l fl as hl s ram 512b u s art1 u s art2 s pi2 / i2 s 2 (1) b x can1 7 ch a nnel s b a ck u p regi s ter 4 ch a nnel s tim1 4 compl. ch a nnel s s cl, s da, s mba i2c1 as af rx,tx, ct s , rt s , u s art 3 temp s en s or pd[15:0] pe[15:0] bkin, etr inp u t as af 4 ch a nnel s , etr 4 ch a nnel s , etr 4 ch a nnel s , etr fclk rc l s s t a nd b y iwdg @v dd @v bat por / pdr su pply su pervi s ion @v dda v dda v ss a @vdda v bat =1. 8 v to 3 .6 v ck as af rx,tx, ct s , rt s , ck as af rx,tx, ct s , rt s , ck as af apb2 : f m a x = 72 mhz nvic s pi1 mo s i,mi s o, s ck,n ss as af 12 b it adc2 if if interf a ce pvd re s et int @v dd ahb toapb1 awu por tamper-rtc/alarm/ s econd out s y s tem 2x( 8 x16 b it) s pi 3 / i2 s3 uart4 rx,tx as af uart5 rx,tx as af tim5 4 ch a nnel s , etr re s et & clockcontrol 12 b it dac1 if if if 12 b it dac 2 @vdda u s b otg f s s of vbu s id dm dp s ram 64 kb gp dma2 5 ch a nnel s tim6 tim7 can1_tx as af s w/jtag tpiu etm tr a ce/trig traceclk traced[0: 3 ] as af as af as af as af as af ethernet mac 10/100 s ram 1.25 kb dpram 2 kb dpram 2 kb mii_txd[ 3 :0]/rmii_txd[1:0] mii_tx_clk/rmii_tx_clk mii_tx_en/rmii_tx_en mii_rxd[ 3 :0]/rmii_rxd[1:0] mii_rx_er/rmii_rx_er mii_rx_clk/rmii_ref_clk mii_rx_dv/rmii_cr s _dv mii_cr s mii_col/rmii_col mdc mdio pp s _out b xcan2 can2_rx as af can2_tx as af a i15411 dac_out1 as af dac_out2 as af @v dda pll gpio port cgpio port d gpio port e v ref+ v ref? mo s i/ s d, mi s o, mck, s ck/ck, n ss /w s as af mo s i/ s d, mi s o, mck, s ck/ck, n ss /w s as af pclk1pclk2 pll2 pll 3 pll 3 dma ethernet ahb
stm32f105xx, stm32f107xx description doc id 15274 rev 4 13/95 2.3.1 arm ? cortex?-m3 core with embedded flash and sram the arm cortex?-m3 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrup ts. the arm cortex?-m3 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. with its embedded arm core, stm32f105xx and stm32f107xx connectivity line family is compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 2.3.2 embedded flash memory 64 to 256 kbytes of embedded flash is available for storing programs and data. 2.3.3 crc (cyclic redundanc y check) calculation unit the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 32-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.3.4 embedded sram 20 to 64 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states. 2.3.5 nested vectored interrupt controller (nvic) the stm32f105xx and stm32f107xx connectivity line embeds a nested vectored interrupt controller able to handle up to 67 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m3) and 16 priority levels. closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency.
description stm32f105xx, stm32f107xx 14/95 doc id 15274 rev 4 2.3.6 external interrupt /event controller (exti) the external interrupt/event controller consists of 20 edge detector lines used to generate interrupt/event requests. each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal apb2 cloc k period. up to 80 gp ios can be connected to the 16 external interrupt lines. 2.3.7 clocks and startup system clock selection is perfor med on startup, however, the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an ex ternal 3-25 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is generated if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). a single 25 mhz crystal can clock the entire system including the ethernet and usb otg fs peripherals. several prescalers and plls allow the configuration of the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. the maximum frequency of the ahb and the high speed apb domains is 72 mhz. the maximum allowed frequency of the low speed apb domain is 36 mhz. refer to figure 48: usb otg fs + ethernet solution on page 89 . the advanced clock controller clocks the core and all peripherals using a single crystal or oscillator. in order to achieve audio class perfor mance, an audio crystal can be used. in this case, the i 2 s master clock can generate all standard sampling frequencies from 8 khz to 96 khz with less than 0.5% a ccuracy error. refer to figure 49: usb otg fs + i 2 s (audio) solution on page 89 . to configure the plls, please refer to table 61 on page 90 , which provides pll configurations according to the application type. 2.3.8 boot modes at startup, boot pins are used to select one of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1, usart2 (remapped), can2 (remapped) or usb otg fs in device mode (dfu: device firmware upgrade). for remapped signals refer to table 5: pin definitions . the usart peripheral o perates with the in ternal 8 mhz oscillator (hsi), however the can and usb otg fs can only function if an exte rnal 8 mhz, 14.7456 mhz or 25 mhz clock (hse) is present. for full details about the boot loader, please refer to an2662.
stm32f105xx, stm32f107xx description doc id 15274 rev 4 15/95 2.3.9 power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v ssa , v dda = 2.0 to 3.6 v: external analog power supplies for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc is used). v dda and v ssa must be connected to v dd and v ss , respectively. v bat = 1.8 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 2.3.10 power supply supervisor the device has an integrated power-on reset (por)/power-down reset (pdr) circuitry. it is always active, and ensures proper operation starting from/down to 2 v. the device remain s in reset mode when v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 2.3.11 voltage regulator the regulator has three operation modes: main (mr), low power (lpr) and power down. mr is used in the nominal regulation mode (run) lpr is used in the stop modes. power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode. 2.3.12 low-power modes the stm32f105xx and stm32f107xx connectivity line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines, the pvd output, the rtc alarm or the usb otg fs wakeup.
description stm32f105xx, stm32f107xx 16/95 doc id 15274 rev 4 standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. 2.3.13 dma the flexible 12-channel general-purpose dmas (7 channels for dma1 and 5 channels for dma2) are able to manage memory-to-memory, peripheral-to-memory and memory-to- peripheral transfers. the two dma controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose, basic and advanced control timers timx, dac, i 2 s and adc. in the stm32f107xx, there is a dma controller dedicated for use with the ethernet (see section 2.3.20: ethernet mac interface with dedicate d dma and ieee 1588 support for more information). 2.3.14 rtc (real-time cl ock) and backup registers the rtc and the backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, and they are not reset when the device wakes up from the standby mode. the real-time clock provides a set of continuo usly running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. it is clocke d by a 32.768 khz external crysta l, resonator or oscillator, the internal low power rc oscillator or the high -speed external clock divided by 128. the internal low-speed rc has a typical frequency of 40 khz. the rtc can be calibrated using an external 512 hz output to compensate for any natural quartz deviation. the rtc features a 32-bit programmable counter for long term measurement using the compare registe r to generate an alarm. a 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 khz. for more information, please refer to an2604: ? stm32f101xx and stm32f103xx rtc calibration ?, available from www.st.com .
stm32f105xx, stm32f107xx description doc id 15274 rev 4 17/95 2.3.15 timers and watchdogs the stm32f105xx and stm32f107xx devices include an advanced-control timer, four general-purpose timers, two basic timers, two watchdog timers and a systick timer. ta bl e 4 compares the features of the general-purpose and basic timers. advanced-control timer (tim1) the advanced control timer (tim1) can be seen as a three-phase pwm multiplexed on 6 channels. it has complementary pwm outputs with programmable inserted dead-times. it can also be seen as a complete general-purpose timer. the 4 independent channels can be used for: input capture output compare pwm generation (edge or center-aligned modes) one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard tim timers which have the same architecture. the advanced control timer can th erefore work together with the tim timers via the timer link feature for synchronization or event chaining. general-purpose timers (timx) there are up to 4 synchronizable standard timers (tim2, tim3, tim4 and tim5) embedded in the stm32f105xx and stm32f107xx connectivity line devices. these timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, pwm or one pulse mode output. this gives up to 16 input captures / output compares / pwms on the largest packages. they can work together with the advanced control timer via the timer link feature for synchronization or event chaining. the counter can be frozen in debug mode. table 4. timer feature comparison timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs tim1 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s timx (tim2, tim3, tim4, tim5) 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim6, tim7 16-bit up any integer between 1 and 65536 ye s 0 n o
description stm32f105xx, stm32f107xx 18/95 doc id 15274 rev 4 any of the standard timers can be used to generate pwm outputs. each of the timers has independent dma request generations. basic timers tim6 and tim7 these timers are mainly used for dac trigger generation. they can also be used as a generic 16-bit time base. independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. window watchdog the window watchdog is based on a 7-bit downcoun ter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrup t capability and the counter can be frozen in debug mode. systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source 2.3.16 i2c bus up to two i2c bus interfaces can operate in multimaster and slave modes. they can support standard and fast modes. they support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). a hardware crc generation/verification is embedded. they can be served by dma and they support smbus 2.0/pmbus. 2.3.17 universal sync hronous/asynchronous receiver transmitters (usarts) the stm32f105xx and stm32f107xx connectivity line embeds three universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3) and two universal asynchronous receiver transmitters (uart4 and uart5). these five interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. the usart1 interface is able to communicate at speeds of up to 4.5 mbit/s. the other available interfaces communicate at up to 2.25 mbit/s.
stm32f105xx, stm32f107xx description doc id 15274 rev 4 19/95 usart1, usart2 and usart3 also provide hardware management of the cts and rts signals, smart card mode (iso 7816 complia nt) and spi-like communication capability. all interfaces can be served by the dma controller except for uart5. 2.3.18 serial perip heral interface (spi) up to three spis are able to communicate up to 18 mbits/s in slave and master modes in full-duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. the hardware crc generation/verification supports basic sd card/mmc/sdhc (a) modes. all spis can be served by the dma controller. 2.3.19 inter-integrated sound (i 2 s) two standard i 2 s interfaces (multiplexed with spi2 and spi3) are available, that can be operated in master or slave mode. these interfaces can be configured to operate with 16/32 bit resolution, as input or output channels. audio sampling frequencies from 8 khz up to 96 khz are supported. when either or both of the i 2 s interfaces is/are configured in master mode, the master clock can be output to the external dac/codec at 256 times the sampling frequency with less than 0.5% accuracy error owing to the advanced clock controller (see section 2.3.7: clocks and startup ). please refer to the ?audio frequency precision? tables provided in the ?serial peripheral interface (spi)? section of the stm32f10xxx reference manual. 2.3.20 ethernet mac interface with dedicated dma and ieee 1588 support peripheral not available on stm32f105xx devices. the stm32f107xx devices provid e an ieee-802.3-2002-complia nt media access controller (mac) for ethernet lan communications through an industry-standard media-independent interface (mii) or a reduced media-independent interface (rmii). the stm32f107xx requires an external physical interface device (phy) to connect to the physical lan bus (twisted-pair, fiber, etc.). the phy is connected to the stm32f107xx mii port using as many as 17 signals (mii) or 9 signals (rmii) and can be clocked using the 25 mhz (mii) or 50 mhz (rmii) output from the stm32f107xx. the stm32f107xx includes the following features: supports 10 and 100 mbit/s rates dedicated dma controller allowing high-speed transfers between the dedicated sram and the descriptors (see the stm32f105xx/stm32f107xx reference manual for details) tagged mac frame support (vlan support) half-duplex (csma/cd) and full-duplex operation mac control sublayer (control frames) support a. sdhc = secure digital high capacity.
description stm32f105xx, stm32f107xx 20/95 doc id 15274 rev 4 32-bit crc generation and removal several address filtering modes for physical and multicast address (multicast and group addresses) 32-bit status code for each transmitted or received frame internal fifos to buffer transmit and receive frames. the transmit fifo and the receive fifo are both 2 kbytes, that is 4 kbytes in total supports hardware ptp (preci sion time protocol) in ac cordance with ieee 1588 with the timestamp comparator connected to the tim2 trigger input triggers interrupt when system time becomes greater than target time 2.3.21 controller area network (can) the two cans are compliant with the 2.0a and b (active) specifications with a bitrate up to 1 mbit/s. they can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. each can has three transmit mailboxes, two receive fifos with 3 stages and 28 shared scalable filter banks (all of them can be used even if one can is used). the 256 bytes of sram which are allocated for each can (512 bytes in total) are not shared with any other peripheral. 2.3.22 universal serial bus on -the-go full-speed (usb otg fs) the stm32f105xx and stm32f107xx connectivity line devices embed a usb otg full- speed (12 mb/s) device/host/otg peripheral with integrated transceivers. the usb otg fs peripheral is compliant with the usb 2.0 specification and with the otg 1.0 specification. it has software-configurable endpoint setting and supports suspend/resume. the usb otg full-speed controller requires a dedicated 48 mhz clock that is generated by a pll connected to the hse oscillato r. the major features are: 1.25 kb of sram used exclusively by the endpoints (not shared with any other peripheral) 4 bidirectional endpoints hnp/snp/ip inside (no need for any external resistor) for otg/host modes, a power switch is needed in case bus-powered devices are connected the sof output can be used to synchronize the external audio dac clock in isochronous mode in accordance with the usb 2.0 specification, the supported transfer speeds are: ? in host mode: full speed and low speed ? in device mode: full speed 2.3.23 gpios (genera l-purpose inputs/outputs) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current- capable except for analog inputs. the i/os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. i/os on apb2 with up to 18 mhz toggling speed
stm32f105xx, stm32f107xx description doc id 15274 rev 4 21/95 2.3.24 remap capability this feature allows the use of a maximum nu mber of peripherals in a given application. indeed, alternate functions are available not only on the default pins but also on other specific pins onto which they are remappable. this has the advantage of making boar d design and port usage much more flexible. for details refer to table 5: pin definitions ; it shows the list of remappable alternate functions and the pins onto which they can be remapped. see the stm32f10xxx reference manual for software considerations. 2.3.25 adcs (analog-to -digital converters) two 12-bit analog-to-digital converters are embedded into stm32f105xx and stm32f107xx connectivity line devices and each adc shares up to 16 external channels, performing conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. additional logic functions embedded in the adc interface allow: simultaneous sample and hold interleaved sample and hold single shunt the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the standard timers (timx) and the advanced-control timer (tim1) can be internally connected to the adc start trigger and injection trigger, respectively, to allow the application to synchronize a/d conversion and timers. 2.3.26 dac (digital-t o-analog converter) the two 12-bit buffered dac channels can be used to convert two digital signals into two analog voltage signal outputs. the chosen design structure is composed of integrat ed resistor strings and an amplifier in inverting configuration. this dual digital interface supports the following features: two dac converters: one for each output channel 8-bit or 12-bit monotonic output left or right data alignment in 12-bit mode synchronized update capability noise-wave generation triangular-wave generation dual dac channel independent or simultaneous conversions dma capability for each channel external triggers for conversion input voltage reference v ref+
description stm32f105xx, stm32f107xx 22/95 doc id 15274 rev 4 eight dac trigger inputs are used in the st m32f105xx and stm32f107xx connectivity line family. the dac channels are triggered through the timer update outputs that are also connected to different dma channels. 2.3.27 temperature sensor the temperature sensor has to generate a voltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.28 serial wire jtag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared respectively with swdio and swclk and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 2.3.29 embedded trace macrocell? the arm ? embedded trace macrocell provides a greater visibilit y of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32f10xxx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using usb, ethernet, or any other high-speed channel. real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools.
stm32f105xx, stm32f107xx pinouts and pin description doc id 15274 rev 4 23/95 3 pinouts and pin description figure 2. stm32f105xxx and stm32f107xxx connectivity line lqfp100 pinout 100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 7574 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 vdd_2 vss_2 nc pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 pb15 pb14 pb13 pb12 pa 3 vss_4 vdd_4 pa 4 pa 5 pa 6 pa 7 pc4pc5 pb0pb1 pb2 pe7 pe8 pe9 pe10 pe11 pe12 pe13 pe14 pe15 pb10 pb11 vss_1 vdd_1 vdd_3 vss_3 pe1 pe0 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pc12 pc11 pc10 pa15 pa14 2627 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 pe2 pe3 pe4 pe5 pe6 vbat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out vss_5 vdd_5 osc_in osc_out nrst pc0pc1 pc2 pc3 vssa vref- vref+ vdda pa 0 - w k u p pa 1 pa 2 ai14391 lqfp100
pinouts and pin description stm32f105xx, stm32f107xx 24/95 doc id 15274 rev 4 figure 3. stm32f105xxx and stm32f107xxx connectivity line lqfp64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 4847 46 45 44 43 4241 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 v bat pc13-tamper-rtc pc14-osc32_in pc15-osc32_out pd0 osc_in pd1 osc_out nrst pc0pc1 pc2 pc3 v ssa v dda pa 0 - w k u p pa 1 pa 2 v dd_3 v ss_3 pb9 pb8 boot0 pb7 pb6 pb5 pb4 pb3 pd2 pc12 pc11 pc10 pa 1 5 pa 1 4 v dd_2 v ss_2 pa 1 3 pa 1 2 pa 1 1 pa 1 0 pa 9 pa 8 pc9 pc8 pc7 pc6 pb15 pb14 pb13 pb12 pa 3 v ss_4 v dd_4 pa 4 pa 5 pa 6 pa 7 pc4pc5 pb0 pb1 pb2 pb10 pb11 v ss_1 v dd_1 lqfp64 ai14392
stm32f105xx, stm32f107xx pinouts and pin description doc id 15274 rev 4 25/95 table 5. pin definitions pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp100 lqfp64 default remap 1 - pe2 i/o ft pe2 traceck 2 - pe3 i/o ft pe3 traced0 3 - pe4 i/o ft pe4 traced1 4 - pe5 i/o ft pe5 traced2 5 - pe6 i/o ft pe6 traced3 61 v bat sv bat 72 pc13-tamper- rtc (5) i/o pc13 (6) tamper-rtc 8 3 pc14-osc32_in (5) i/o pc14 (6) osc32_in 94 pc15- osc32_out (5) i/o pc15 (6) osc32_out 10 - v ss_5 sv ss_5 11 - v dd_5 sv dd_5 12 5 osc_in i osc_in 13 6 osc_out o osc_out 14 7 nrst i/o nrst 15 8 pc0 i/o pc0 adc12_in10 16 9 pc1 i/o pc1 adc12_in11/ eth_mdc 17 10 pc2 i/o pc2 adc12_in12/ eth_mii_txd2 18 11 pc3 i/o pc3 adc12_in13/ eth_mii_tx_clk 19 12 v ssa sv ssa 20 - v ref- sv ref- 21 - v ref+ sv ref+ 22 13 v dda sv dda 23 14 pa0-wkup i/o pa0 wkup/usart2_cts (7) adc12_in0/tim2_ch1_etr tim5_ch1/ eth_mii_crs_wkup 2 4 1 5 pa 1 i / o pa 1 usart2_rts (7) / adc12_in1/ tim5_ch2 /tim2_ch2 (7) / eth_mii_rx_clk/ eth_rmii_ref_clk 2 5 1 6 pa 2 i / o pa 2 usart2_tx (7) / tim5_ch3/adc12_in2/ tim2_ch3 (7) / eth_mdio
pinouts and pin description stm32f105xx, stm32f107xx 26/95 doc id 15274 rev 4 2 6 1 7 pa 3 i / o pa 3 usart2_rx (7) / tim5_ch4/adc12_in3 / tim2_ch4 (7) / eth_mii_col 27 18 v ss_4 sv ss_4 28 19 v dd_4 sv dd_4 2 9 2 0 pa 4 i / o pa 4 spi1_nss (7) /dac_out1 / usart2_ck (7) / adc12_in4 spi3_nss 3 0 2 1 pa 5 i / o pa 5 spi1_sck (7) / dac_out2 / adc12_in5 3 1 2 2 pa 6 i / o pa 6 spi1_miso (7) /adc12_in6 / tim3_ch1 (7) tim1_bkin 3 2 2 3 pa 7 i / o pa 7 spi1_mosi (7) /adc12_in7 / tim3_ch2 (7) / eth_mii_rx_dv/ eth_rmii_crs_dv tim1_ch1n 33 24 pc4 i/o pc4 adc12_in14 / eth_mii_rxd0 / eth_rmii_rxd0 34 25 pc5 i/o pc5 adc12_in15 / eth_mii_rxd1 / eth_rmii_rxd1 35 26 pb0 i/o pb0 adc12_in8/tim3_ch3/ eth_mii_rxd2 tim1_ch2n 36 27 pb1 i/o pb1 adc12_in9 / tim3_ch4 (7) / eth_mii_rxd3 tim1_ch3n 37 28 pb2 i/o ft pb2/boot1 38 - pe7 i/o ft pe7 tim1_etr 39 - pe8 i/o ft pe8 tim1_ch1n 40 - pe9 i/o ft pe9 tim1_ch1 41 - pe10 i/o ft pe10 tim1_ch2n 42 - pe11 i/o ft pe11 tim1_ch2 43 - pe12 i/o ft pe12 tim1_ch3n 44 - pe13 i/o ft pe13 tim1_ch3 45 - pe14 i/o ft pe14 tim1_ch4 46 - pe15 i/o ft pe15 tim1_bkin 47 29 pb10 i/o ft pb10 i2c2_scl/usart3_tx (7) / eth_mii_rx_er tim2_ch3 48 30 pb11 i/o ft pb11 i2c2_sda/usart3_rx (7) / eth_mii_tx_en/ eth_rmii_tx_en tim2_ch4 table 5. pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp100 lqfp64 default remap
stm32f105xx, stm32f107xx pinouts and pin description doc id 15274 rev 4 27/95 49 31 v ss_1 sv ss_1 50 32 v dd_1 sv dd_1 51 33 pb12 i/o ft pb12 spi2_nss/i2s2_ws/ i2c2_ smba / usart3_ck (7) / tim1_bkin (7) / can2_rx/ eth_mii_txd0/ eth_rmii_txd0 52 34 pb13 i/o ft pb13 spi2_sck / i2s2_ck / usart3_cts (7) / tim1_ch1n / can2_tx / eth_mii_txd1/ eth_rmii_txd1 53 35 pb14 i/o ft pb14 spi2_miso / tim1_ch2n / usart3_rts (7) 54 36 pb15 i/o ft pb15 spi2_mosi / i2s2_sd / tim1_ch3n (7) 55 - pd8 i/o ft pd8 usart3_tx/ eth_mii_rx_dv 56 - pd9 i/o ft pd9 usart3_rx/ eth_mii_rx_d0 57 - pd10 i/o ft pd10 usart3_ck/ eth_mii_rx_d1 58 - pd11 i/o ft pd11 usart3_cts/ eth_mii_rx_d2 59 - pd12 i/o ft pd12 tim4_ch1 / usart3_rts/ eth_mii_rx_d3 60 - pd13 i/o ft pd13 tim4_ch2 61 - pd14 i/o ft pd14 tim4_ch3 62 - pd15 i/o ft pd15 tim4_ch4 63 37 pc6 i/o ft pc6 i2s2_mck/ tim3_ch1 64 38 pc7 i/o ft pc7 i2s3_mck tim3_ch2 65 39 pc8 i/o ft pc8 tim3_ch3 66 40 pc9 i/o ft pc9 tim3_ch4 6 7 4 1 pa 8 i / o f t pa 8 usart1_ck/otg_fs_sof / tim1_ch1 (7) /mco 6 8 4 2 pa 9 i / o f t pa 9 usart1_tx (7) / tim1_ch2 (7) / otg_fs_vbus 69 43 pa10 i/o ft pa10 usart1_rx (7) / tim1_ch3 (7) /otg_fs_id table 5. pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp100 lqfp64 default remap
pinouts and pin description stm32f105xx, stm32f107xx 28/95 doc id 15274 rev 4 70 44 pa11 i/o ft pa11 usart1_cts / can1_rx / tim1_ch4 (7) /otg_fs_dm 71 45 pa12 i/o ft pa12 usart1_rts / otg_fs_dp / can1_tx (7) / tim1_etr (7) 72 46 pa13 i/o ft jtms-swdio pa 1 3 73 - not connected 74 47 v ss_2 sv ss_2 75 48 v dd_2 sv dd_2 76 49 pa14 i/o ft jtck-swclk pa14 77 50 pa15 i/o ft jtdi spi3_nss / i2s3_ws tim2_ch1_etr / pa15 spi1_nss 78 51 pc10 i/o ft pc10 uart4_tx usart3_tx/ spi3_sck 79 52 pc11 i/o ft pc11 uart4_rx usart3_rx/ spi3_miso 80 53 pc12 i/o ft pc12 uart5_tx usart3_ck/ spi3_mosi 81 5 pd0 i/o ft osc_in (8) can1_rx 82 6 pd1 i/o ft osc_out (8) can1_tx 83 54 pd2 i/o ft pd2 tim3_etr / uart5_rx 84 - pd3 i/o ft pd3 usart2_cts 85 - pd4 i/o ft pd4 usart2_rts 86 - pd5 i/o ft pd5 usart2_tx 87 - pd6 i/o ft pd6 usart2_rx 88 - pd7 i/o ft pd7 usart2_ck 89 55 pb3 i/o ft jtdo spi3_sck / i2s3_ck pb3 / traceswo/ tim2_ch2 / spi1_sck 90 56 pb4 i/o ft njtrst spi3_miso pb4 / tim3_ch1/ spi1_miso 91 57 pb5 i/o pb5 i2c1_ smba / spi3_mosi / eth_pps_out / i2s3_sd tim3_ch2/spi1_mosi/ can2_rx 92 58 pb6 i/o ft pb6 i2c1_scl (7) /tim4_ch1 (7) usart1_tx/can2_tx 93 59 pb7 i/o ft pb7 i2c1_sda (7) /tim4_ch2 (7) usart1_rx 94 60 boot0 i boot0 95 61 pb8 i/o ft pb8 tim4_ch3 (7) / eth_mii_txd3 i2c1_scl/can1_rx 96 62 pb9 i/o ft pb9 tim4_ch4 (7) i2c1_sda / can1_tx table 5. pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp100 lqfp64 default remap
stm32f105xx, stm32f107xx pinouts and pin description doc id 15274 rev 4 29/95 97 - pe0 i/o ft pe0 tim4_etr 98 - pe1 i/o ft pe1 99 63 v ss_3 sv ss_3 100 64 v dd_3 sv dd_3 1. i = input, o = output, s = supply. 2. ft = 5 v tolerant. all i/os are v dd capable. 3. function availability depends on the chosen device. 4. if several peripherals share the same i/o pin, to avoid conflict between these alte rnate functions only one peripheral should be enabled at a time through the peri pheral clock enable bit (in the correspondi ng rcc peripheral clock enable register). 5. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpios pc13 to pc15 in output mode is limited: the speed should not exceed 2 mhz with a maximum load of 30 pf and these ios must not be used as a current source (e.g. to drive an led). 6. main function after the first backup domain power-up. later on, it depends on the contents of the backup registers even after reset (because these registers are not reset by the main reset). for details on how to manage these ios, refer to the battery backup domain and bkp register description sections in the stm32f10xxx reference manual, available from the stmicroelectronics website: www.st.com. 7. this alternate function can be remapped by software to some other port pins (if available on the used package). for more details, refer to the alternate function i/o and debug conf iguration section in the st m32f10xxx reference manual, available from the stmicroel ectronics website: www.st.com. 8. for the lqfp64 package, the pins number 5 and 6 are c onfigured as osc_in/osc_out after reset, however the functionality of pd0 and pd1 can be remapped by software on these pins. for the lqfp100 package, pd0 and pd1 are available by default, so there is no need for remapping. fo r more details, refer to alternate function i/o and debug configuration section in the stm32f10xxx reference manual. table 5. pin definitions (continued) pins pin name type (1) i / o level (2) main function (3) (after reset) alternate functions (4) lqfp100 lqfp64 default remap
memory mapping stm32f105xx, stm32f107xx 30/95 doc id 15274 rev 4 4 memory mapping the memory map is shown in figure 4 . figure 4. memory map 512-m b yte b lock 7 cortex-m 3 ' s intern a l peripher a l s 512-m b yte b lock 6 not us ed 512-m b yte b lock 5 not us ed 512-m b yte b lock 4 not us ed 512-m b yte b lock 3 not us ed 512-m b yte b lock 2 peripher a l s 512-m b yte b lock 1 s ram 0x0000 0000 0x1fff ffff 0x2000 0000 0x 3 fff ffff 0x4000 0000 0x5fff ffff 0x6000 0000 0x7fff ffff 0x 8 000 0000 0xafff ffff 0xb000 0000 0xbfff ffff 0xc000 0000 0xdfff ffff 0xe000 0000 0xffff ffff 512-m b yte b lock 0 code fl as h 0x0 8 04 0000 0x1fff afff 0x1fff b000 - 0x1fff f7ff 0x0 8 00 0000 0x0 8 0 3 ffff 0x0004 0000 0x07ff ffff 0x0000 0000 0x000 3 ffff s y s tem memory re s erved re s erved ali as ed to fl as h or s y s tem memory depending on boot pin s s ram ( a li as ed b y b it- ba nding) re s erved 0x2000 0000 0x2000 ffff 0x2001 0000 0x 3 fff ffff rtc wwdg 0x4000 2 8 00 - 0x4000 2bff iwdg re s erved s pi2/i2 s 2 s pi 3 /i2 s3 re s erved 0x4000 2c00 - 0x4000 2fff 0x4000 3 000 - 0x4000 33 ff 0x4000 3 400 - 0x4000 3 7ff 0x4000 38 00 - 0x4000 3 bff 0x4000 3 c00 - 0x4000 3 fff 0x4000 4000 - 0x4000 4 3 ff u s art2 0x4000 4400 - 0x4000 47ff u s art 3 0x4000 4 8 00 - 0x4000 4bff uart4 0x4000 4c00 - 0x4000 4fff uart5 0x4000 5000 - 0x4000 5 3 ff i2c1 0x4000 5400 - 0x4000 57ff i2c2 0x4000 5 8 00 - 0x4000 5bff re s erved 0x4000 5c00 - 0x4000 6 3 ff 0x4000 6400 - 0x4000 67ff b xcan1 b xcan2 0x4000 6 8 00 - 0x4000 6bff bkp 0x4000 6c00 - 0x4000 6fff pwr 0x4000 7000 - 0x4000 7 3 ff dac 0x4000 7400 - 0x4000 77ff afio 0x4001 0000 - 0x4001 3 fff exti 0x4001 0400 - 0x4001 07ff port a 0x4001 0 8 00 - 0x4001 0bff port b 0x4001 0c00 - 0x4001 0fff port c 0x4001 1000 - 0x4001 1 3 ff port d 0x4001 1400 - 0x4001 17ff port e 0x4001 1 8 00 - 0x4001 1bff re s erved 0x4001 1c00 - 0x4001 2 3 ff adc1 0x4001 2400 - 0x4001 27ff adc2 0x4001 2 8 00 - 0x4001 2bff tim1 0x4001 2c00 - 0x4001 2fff s pi1 0x4001 3 000 - 0x4001 33 ff re s erved 0x4001 3 400 - 0x4001 3 7ff u s art1 0x4001 38 00 - 0x4001 3 bff re s erved 0x4001 3 c00 - 0x4001 ffff dma2 0x4002 0400 - 0x4002 07ff re s erved 0x4002 1400 - 0x4002 1fff fl as h interf a ce 0x4002 2000 - 0x4002 2 3 ff re s erved 0x4002 2400 - 0x4002 2fff crc 0x4002 3 000 - 0x4002 33 ff re s erved 0x4002 3 400 - 0x4002 7fff ethernet 0x4002 8 000 - 0x4002 9fff re s erved 0x400 3 0000 - 0x4fff ffff u s b otg f s 0x5000 0000 - 0x5000 0 3 ff re s erved 0x5000 0400 - 0x5fff ffff a i15412 b 0x4002 0 8 00 - 0x4002 0fff 0x4002 1000 - 0x4002 1 3 ff re s erved rcc dma1 0x4002 0000 - 0x4002 0 3 ff re s erved 0x4000 7 8 00 - 0x4000 ffff apb2 ahb 0x4000 1 8 00 - 0x4000 27ff 0x4000 0 8 00 - 0x4000 0bff 0x4000 0c00 - 0x4000 0fff 0x4000 1000 - 0x4000 1 3 ff 0x4000 1400 - 0x4000 17ff0x4000 0000 - 0x4000 0 3 ff 0x4000 0400 - 0x4000 07ff re s erved tim7tim6 tim5 tim4 tim 3 tim2 apb1 option b yte s 0x1fff f 8 00 - 0x1fff ffff
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 31/95 5 electrical characteristics 5.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 5.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, desi gn simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 6 ). 5.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v (for the 2v d v dd d 3.6 v voltage range). they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 6 ) . 5.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 5 . 5.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 6 . figure 5. pin loading condition s figure 6. pin input voltage ai15664 c = 50 pf stm32f10xxx pin ai15665 stm32f10xxx pin v in
electrical characteristics stm32f105xx, stm32f107xx 32/95 doc id 15274 rev 4 5.1.6 power supply scheme figure 7. power supply scheme caution: in figure 7 , the 4.7 f capacitor must be connected to v dd3 . 5.1.7 current con sumption measurement figure 8. current consumption measurement scheme ai14125d v dd 1/2/3/4/5 an alo g: rcs, pll, ... po wer swi tch v bat gp i/o s out in kernel logic (cpu, digital & memories) backup circuitry (osc32k,rtc, backup registers) wake-up logic 5 100 nf + 1 4.7 f 1.8-3.6v regulator v ss 1/2/3/4/5 v dda v ref+ v ref- v ssa adc level shifter io logic v dd 10 nf + 1 f v ref 10 nf + 1 f v dd ai14126 v bat v dd v dda i dd _v bat i dd
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 33/95 5.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 6: voltage characteristics , table 7: current characteristics , and table 8: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 6. voltage characteristics symbol ratings min max unit v dd ?v ss external main supply voltage (including v dda and v dd ) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. ?0.3 4.0 v v in input voltage on five volt tolerant pin (2) 2. i inj(pin) must never be exceeded (see table 7: current characteristics ). this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v in max while a negative injection is induced by v in < v ss . v ss 0.3 +5.5 input voltage on any other pin (2) v ss 0.3 v dd +0.3 | ' v ddx | variations between different v dd power pins 50 mv |v ssx v ss | variations between all the different ground pins 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 5.3.11: absolute maximum ratings (electrical sensitivity) table 7. current characteristics symbol ratings max. unit i vdd total current into v dd /v dda power lines (source) (1) 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 150 ma i vss total current out of v ss ground lines (sink) (1) 150 i io output current sunk by any i/o and control pin 25 output current source by any i/os and control pin 25 i inj(pin) (2)(3) 2. i inj(pin) must never be exceeded. this is implicitly insured if v in maximum is respected. if v in maximum cannot be respected, the injection current must be limited externally to the i inj(pin) value. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . 3. negative injection disturbs the analog performance of the device. see note in section 5.3.16: 12-bit adc characteristics . injected current on nrst pin 5 injected current on hse osc_in and lse osc_in pins 5 injected current on any other pin (4) 4. when several inputs are submitted to a current injection, the maximum 6 i inj(pin) is the absolute sum of the positive and negative injected currents (insta ntaneous values). thes e results are based on characterization with 6 i inj(pin) maximum current injection on fo ur i/o port pins of the device. 5 6 i inj(pin) (2) total injected current (sum of all i/o and control pins) (4) 25
electrical characteristics stm32f105xx, stm32f107xx 34/95 doc id 15274 rev 4 5.3 operating conditions 5.3.1 general operating conditions table 8. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c table 9. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 72 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 72 v dd standard operating voltage 2 3.6 v v dda (1) 1. when the adc is used, refer to table 51: adc characteristics . analog operating voltage (adc not used) must be the same potential as v dd (2) 2. it is recommended to power v dd and v dda from the same source. a maximum difference of 300 mv between v dd and v dda can be tolerated during power-up and operation. 23 . 6 v analog operating voltage (adc used) 2.4 3.6 v bat backup operating voltage 1.8 3.6 v p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (3) 3. if t a is lower, higher p d values are allowed as long as t j does not exceed t j max. lqfp100 434 mw lqfp64 444 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (4) 4. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t j max. ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (4) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 35/95 5.3.2 operating conditions at power-up / power-down subject to general operating conditions for t a . table 10. operating conditions at power-up / power-down 5.3.3 embedded reset and power control block characteristics the parameters given in ta bl e 1 1 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . symbol parameter conditions min max unit t vdd v dd rise time rate 0 f s/v v dd fall time rate 20 f table 11. embedded reset and power control block characteristics symbol parameter conditions min typ max unit v pvd programmable voltage detector level selection pls[2:0]=000 (rising edge) 2.1 2.18 2.26 v pls[2:0]=000 (falling edge) 2 2.08 2.16 v pls[2:0]=001 (rising edge) 2.19 2.28 2.37 v pls[2:0]=001 (falling edge) 2.09 2.18 2.27 v pls[2:0]=010 (rising edge) 2.28 2.38 2.48 v pls[2:0]=010 (falling edge) 2.18 2.28 2.38 v pls[2:0]=011 (rising edge) 2.38 2.48 2.58 v pls[2:0]=011 (falling edge) 2.28 2.38 2.48 v pls[2:0]=100 (rising edge) 2.47 2.58 2.69 v pls[2:0]=100 (falling edge) 2.37 2.48 2.59 v pls[2:0]=101 (rising edge) 2.57 2.68 2.79 v pls[2:0]=101 (falling edge) 2.47 2.58 2.69 v pls[2:0]=110 (rising edge) 2.66 2.78 2.9 v pls[2:0]=110 (falling edge) 2.56 2.68 2.8 v pls[2:0]=111 (rising edge) 2.76 2.88 3 v pls[2:0]=111 (falling edge) 2.66 2.78 2.9 v v pvdhyst (2) pvd hysteresis 100 mv v por/pdr power on/power down reset threshold falling edge 1.8 (1) 1. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (2) pdr hysteresis 40 mv t rsttempo (2) 2. guaranteed by design, not tested in production. reset temporization 1 2.5 4.5 ms
electrical characteristics stm32f105xx, stm32f107xx 36/95 doc id 15274 rev 4 5.3.4 embedded reference voltage the parameters given in ta bl e 1 2 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . 5.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pin loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 8: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to dhrystone 2.1 code. maximum current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled except when explicitly mentioned the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above) prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /2, f pclk2 = f hclk the parameters given in ta bl e 1 3 , ta bl e 1 4 and ta bl e 1 5 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 12. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.20 1.26 v ?40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefint (1) 1. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the internal reference voltage 5.1 17.1 (2) 2. guaranteed by design, not tested in production. s v rerint (2) internal reference voltage spread over the temperature range v dd = 3 v 10 mv 10 mv t coeff (2) temperature coefficient 100 ppm/c
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 37/95 table 13. maximum current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk max (1) 1. based on characterization , not tested in production. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 68 68.4 ma 48 mhz 49 49.2 36 mhz 38.7 38.9 24 mhz 27.3 27.9 16 mhz 20.2 20.5 8 mhz 10.2 10.8 external clock (3) , all peripherals disabled 72 mhz 32.7 32.9 48 mhz 25 25.2 36 mhz 20.3 20.6 24 mhz 14.8 15.1 16 mhz 11.2 11.7 8 mhz 6.6 7.2 table 14. maximum current consumption in run mode, code with data processing running from ram symbol parameter conditions f hclk max (1) 1. based on characterization, tested in production at v dd max, f hclk max.. unit t a = 85 c t a = 105 c i dd supply current in run mode external clock (2) , all peripherals enabled 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 65.5 66 ma 48 mhz 45.4 46 36 mhz 35.5 36.1 24 mhz 25.2 25.6 16 mhz 18 18.5 8 mhz 10.5 11 external clock (3) , all peripherals disabled 72 mhz 31.4 31.9 48 mhz 27.8 28.2 36 mhz 17.6 18.3 24 mhz 13.1 13.8 16 mhz 10.2 10.9 8 mhz 6.1 7.8
electrical characteristics stm32f105xx, stm32f107xx 38/95 doc id 15274 rev 4 table 15. maximum current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk max (1) unit t a = 85 c t a = 105 c i dd supply current in sleep mode external clock (2) , all peripherals enabled 72 mhz 48.4 49 ma 48 mhz 33.9 34.4 36 mhz 26.7 27.2 24 mhz 19.3 19.8 16 mhz 14.2 14.8 8 mhz 8.7 9.1 external clock (3) , all peripherals disabled 72 mhz 10.1 10.6 48 mhz 8.3 8.75 36 mhz 7.5 8 24 mhz 6.6 7.1 16 mhz 6 6.5 8 mhz 2.5 3 1. based on characterization, tested in production at v dd max and f hclk max with peripherals enabled. 2. external clock is 8 mhz and pll is on when f hclk > 8 mhz. table 16. typical and maximum current consumptions in stop and standby modes symbol parameter conditions typ (1) max unit v dd /v bat = 2.0 v v dd /v bat = 2.4 v v dd /v bat = 3.3 v t a = 85 c t a = 105 c i dd supply current in stop mode regulator in run mode, low-speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 32 33 600 1300 a regulator in low power mode, low- speed and high-speed internal rc oscillators and high-speed oscillator off (no independent watchdog) 25 26 590 1280 supply current in standby mode low-speed internal rc oscillator and independent watchdog on 33 . 8-- low-speed internal rc oscillator on, independent watchdog off 2.8 3.6 - - low-speed internal rc oscillator and independent watchdog off, low- speed oscillator and rtc off 1.9 2.1 5 (2) 6.5 (2) i dd_vbat backup domain supply current low-speed oscillator and rtc on 1.1 1.2 1.4 2.1 (2) 2.3 (2) 1. typical values are measured at t a = 25 c. 2. based on characterization, not tested in production.
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 39/95 figure 9. typical current consumption on v bat with rtc on vs. temperature at different v bat values figure 10. typical current consumption in stop mode with regulator in run mode versus temperature at different v dd values 0 0.5 1 1.5 2 2.5 ?40 c 25 c 70 c 8 5 c 105 c temper a t u re (c) con su mption ( a) 1. 8 v 2 v 2.4 v 3 . 3 v 3 .6 v a i17 3 29 0.00 100.00 200.00 3 00.00 400.00 500.00 600.00 700.00 8 00.00 900.00 ?40 c 25 c 8 5 c 105 c temper a t u re (c) con su mption ( a) 3 .6 v 3 . 3 v 3 v 2.7 v 2.4 v a i17122
electrical characteristics stm32f105xx, stm32f107xx 40/95 doc id 15274 rev 4 figure 11. typical current consumption in stop mode with regulator in low-power mode versus temperature at different v dd values figure 12. typical current consumption in standby mode versus temperature at different v dd values typical current consumption the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load). all peripherals are disabled except if it is explicitly mentioned. the flash access time is adjusted to f hclk frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) when the peripherals are enabled f pclk1 = f hclk /4, f pclk 2 = f hclk /2, f adcclk = f pclk2 /4 0.00 100.00 200.00 3 00.00 400.00 500.00 600.00 700.00 8 00.00 900.00 ?40 c 25 c 8 5 c 105 c temperature (c) con s umption (a) 3 .6 v 3 . 3 v 3 v 2.7 v 2.4 v a i1712 3 0.00 0.50 1.00 1.50 2.00 2.50 3 .00 3 .50 4.00 4.50 ?40 c 25 c 8 5 c 105 c temperature (c) con s umption (a) 3 .6 v 3 . 3 v 3 v 2.7 v 2.4 v a i17124
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 41/95 table 17. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in run mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 47.3 28.3 ma 48 mhz 32 19.6 36 mhz 24.6 15.4 24 mhz 16.8 10.6 16 mhz 11.8 7.4 8 mhz 5.9 3.7 4 mhz 3.7 2.9 2 mhz 2.5 2 1 mhz 1.8 1.53 500 khz 1.5 1.3 125 khz 1.3 1.2 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 36 mhz 23.9 14.8 ma 24 mhz 16.1 9.7 16 mhz 11.1 6.7 8 mhz 5.6 3.8 4 mhz 3.1 2.1 2 mhz 1.8 1.3 1 mhz 1.16 0.9 500 khz 0.8 0.67 125 khz 0.6 0.5
electrical characteristics stm32f105xx, stm32f107xx 42/95 doc id 15274 rev 4 on-chip peripheral current consumption the current consumption of the on-chip peripherals is given in ta bl e 1 9 . the mcu is placed under the following conditions: all i/o pins are in input mode with a static value at v dd or v ss (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with one peripheral clocked on (with only the clock applied) ambient operating temperature and v dd supply voltage conditions summarized in ta bl e 6 table 18. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ (1) 1. typical values are measures at t a = 25 c, v dd = 3.3 v. unit all peripherals enabled (2) 2. add an additional power consumption of 0.8 ma per adc for the analog part. in applications, this consumption occurs only while the adc is on (adon bit is set in the adc_cr2 register). all peripherals disabled i dd supply current in sleep mode external clock (3) 3. external clock is 8 mhz and pll is on when f hclk > 8 mhz. 72 mhz 28.2 6 ma 48 mhz 19 4.2 36 mhz 14.7 3.4 24 mhz 10.1 2.5 16 mhz 6.7 2 8 mhz 3.2 1.3 4 mhz 2.3 1.2 2 mhz 1.7 1.16 1 mhz 1.5 1.1 500 khz 1.3 1.05 125 khz 1.2 1.05 running on high speed internal rc (hsi), ahb prescaler used to reduce the frequency 36 mhz 13.7 2.6 24 mhz 9.3 1.8 16 mhz 6.3 1.3 8 mhz 2.7 0.6 4 mhz 1.6 0.5 2 mhz 1 0.46 1 mhz 0.8 0.44 500 khz 0.6 0.43 125 khz 0.5 0.42
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 43/95 table 19. peripheral current consumption (1) 1. f hclk = 72 mhz, f apb1 = f hclk /2, f apb2 = f hclk , default prescaler value for each peripheral. peripheral typical consumption at 25 c unit ahb eth_mac 5.2 ma otg_fs 7.7 apb1 tim2 1.5 tim3 1.5 tim4 1.5 tim5 1.5 tim6 0.6 tim7 0.3 spi2 0.2 usart2 0.5 usart3 0.5 uart4 0.5 uart5 0.5 i2c1 0.5 i2c2 0.5 can1 0.8 can2 0.8 dac 0.4 apb2 gpio a 0.5 ma gpio b 0.5 gpio c 0.5 gpio d 0.5 gpio e 0.5 adc1 (2) 2. specific conditions for adc: f hclk = 56 mhz, f apb1 = f hclk /2, f apb2 = f hclk , f adcclk = f apb2/4 , adon bit in the adc_cr2 register is set to 1. 2.1 adc2 (2) 2.0 tim1 1.7 spi1 0.4 usart1 0.9
electrical characteristics stm32f105xx, stm32f107xx 44/95 doc id 15274 rev 4 5.3.6 external cloc k source characteristics high-speed external user clock generated from an external source the characteristics given in ta b l e 2 0 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 9 . low-speed external user clock generated from an external source the characteristics given in ta b l e 2 1 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in ta b l e 9 . table 20. high-speed external user clock characteristics symbol parameter conditions min typ max unit f hse_ext external user clock source frequency (1) 185 0 m h z v hseh osc_in input pin high level voltage 0.7v dd v dd v v hsel osc_in input pin low level voltage v ss 0.3v dd t w(hse) t w(hse) osc_in high or low time (1) 1. guaranteed by design, not tested in production. 16 ns t r(hse) t f(hse) osc_in rise or fall time (1) 20 c in(hse) osc_in input capacitance (1) 5p f ducy (hse) duty cycle 45 55 % i l osc_in input leakage current v ss d v in d v dd 1 a table 21. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd v dd v v lsel osc32_in input pin low level voltage v ss 0.3v dd t w(lse) t w(lse) osc32_in high or low time (1) 450 ns t r(lse) t f(lse) osc32_in rise or fall time (1) 50 c in(lse) osc32_in input capacitance (1) 5p f ducy (lse) duty cycle 30 70 % i l osc32_in input leakage current v ss d v in d v dd 1 a
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 45/95 figure 13. high-speed external clock source ac timing diagram figure 14. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 3 to 25 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 2 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai14127b os c _i n external stm32f10xxx clock source v hseh t f(hse) t w(hse) i l 90%10% t hse t t r(hse) t w(hse) f hse_ext v hsel ai14140c osc32_in external stm32f10xxx clock source v lseh t f(lse) t w(lse) i l 90%10% t lse t t r(lse) t w(lse) f lse_ext v lsel
electrical characteristics stm32f105xx, stm32f107xx 46/95 doc id 15274 rev 4 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see figure 15 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . refer to the application note an28 67 ?oscillator design guide for st microcontrollers? available fr om the st website www.st.com. figure 15. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 3 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal table 22. hse 3-25 mhz oscillator characteristics (1) (2) 1. resonator characte ristics given by the crystal/ ceramic resonator manufacturer. 2. based on characterization , not tested in production. symbol parameter conditions min typ max unit f osc_in oscillator frequency 3 25 mhz r f feedback resistor 200 k : c recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the relatively low value of the rf resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and t he bias condition change. however, it is recommended to take this point into account if the mcu is used in tough humidity conditions. r s = 30 : 30 pf i 2 hse driving current v dd = 3.3 v, v in =v ss with 30 pf load 1m a g m oscillator transconductance startup 25 ma/v t su(hse (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal resonat or and it can vary significantly with the crystal manufacturer startup time v dd is stabilized 2 ms ai14128b osc_ou t osc_in f hse c l1 r f stm32f10xxx 8 mh z resonator resonator withintegrated capacitors bias controlled gain r ext (1) c l2
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 47/95 resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). note: for c l1 and c l2 it is recommended to use high-quality external ceramic capacitors in the 5 pf to 15 pf range selected to match the requirements of the crystal or resonator (see figure 16 ). c l1 and c l2, are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . load capacitance c l has the following formula: c l = c l1 x c l2 / ( c l1 + c l2 ) + c stray where c stray is the pin capacitance and board or trace pcb-related capacitance. typically, it is between 2 pf and 7 pf. caution: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l d 7 pf. never use a resonator with a load capacitance of 12.5 pf. example: if you choose a resonator with a load capacitance of c l = 6 pf, and c stray = 2 pf, then c l1 = c l2 = 8 pf. figure 16. typical application with a 32.768 khz crystal table 23. lse oscillator characteristics (f lse = 32.768 khz) (1) 1. based on characterization , not tested in production. symbol parameter conditions min typ max unit r f feedback resistor 5 m : c (2) 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. recommended load capacitance versus equivalent serial resistance of the crystal (r s ) (3) 3. the oscillator selection can be optimized in terms of supply current using an hi gh quality resonator with small r s value for example msiv-tin32.768khz. refer to crystal manufacturer for more details r s = 30 k : 15 pf i 2 lse driving current v dd = 3.3 v, v in = v ss 1.4 a g m oscillator transconductance 5 a/v t su(lse) (4) 4. t su(lse) is the startup time measured from the mom ent it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is measured for a standard cr ystal resonator and it can vary significantly with t he crystal manufacturer startup time v dd is stabilized 3 s ai14129b osc32_ou t osc32_in f lse c l1 r f stm32f10xxx 32.768 kh z resonator resonator withintegrated capacitors bias controlled gain c l2
electrical characteristics stm32f105xx, stm32f107xx 48/95 doc id 15274 rev 4 5.3.7 internal clock source characteristics the parameters given in ta bl e 2 4 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . high-speed internal (hsi) rc oscillator low-speed internal (lsi) rc oscillator wakeup time from low-power mode the wakeup times given in ta b l e 2 6 is measured on a wakeup phase with a 8-mhz hsi rc oscillator. the clock source used to wake up the device depe nds from the current operating mode: stop or standby mode: the cloc k source is the rc oscillator sleep mode: the clock source is the clock that was set before entering sleep mode. table 24. hsi oscillator characteristics (1) 1. v dd = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency 8 mhz acc hsi accuracy of the hsi oscillator user-trimmed with the rcc_cr register (2) 2. refer to application note an2868 ?stm32f10xxx internal rc oscillator (hsi) calibrat ion? available from the st website www.st.com. 1 (3) 3. guaranteed by design, not tested in production. % factory- calibrated (4) 4. based on characterization , not tested in production. t a = ?40 to 105 c ?2 2.5 % t a = ?10 to 85 c ?1.5 2.2 % t a = 0 to 70 c ?1.3 2 % t a = 25 c ?1.1 1.8 % t su(hsi) (4) hsi oscillator startup time 12 s i dd(hsi) (4) hsi oscillator power consumption 80 100 a table 25. lsi oscillator characteristics (1) 1. v dd = 3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi (2) 2. based on characterization , not tested in production. frequency 30 40 60 khz t su(lsi) (3) 3. guaranteed by design, not tested in production. lsi oscillator startup time 85 s i dd(lsi) (3) lsi oscillator power consumption 0.65 1.2 a
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 49/95 all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . 5.3.8 pll, pll2 and pll3 characteristics the parameters given in ta bl e 2 7 and ta b l e 2 8 are derived from tests performed under temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 26. low-power mode wakeup timings symbol parameter typ unit t wusleep (1) 1. the wakeup times are measured from the wakeup even t to the point in which the user application code reads the first instruction. wakeup from sleep mode 1.8 s t wustop (1) wakeup from stop mode (regulator in run mode) 3.6 s wakeup from stop mode (regulator in low power mode) 5.4 t wustdby (1) wakeup from standby mode 50 s table 27. pll characteristics symbol parameter min (1) 1. based on characterization , not tested in production. max (1) unit f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 31 2m h z pulse width at high level 30 ns f pll_out pll multiplier output clock 18 72 mhz f vco_out pll vco output 36 144 mhz t lock pll lock time 350 s jitter cycle-to-cycle jitter 300 ps table 28. pll2 and pll3 characteristics symbol parameter min (1) 1. based on characterization , not tested in production. max (1) unit f pll_in pll input clock (2) 2. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 35m h z pulse width at high level 30 ns f pll_out pll multiplier output clock 40 74 mhz f vco_out pll vco output 80 148 mhz t lock pll lock time 350 s jitter cycle-to-cycle jitter 400 ps
electrical characteristics stm32f105xx, stm32f107xx 50/95 doc id 15274 rev 4 5.3.9 memory characteristics flash memory the characteristics are given at t a = ? 40 to 105 c unless otherwise specified. table 30. flash memory endurance and data retention 5.3.10 emc characteristics susceptibility tests ar e performed on a sample basis during device characterization. table 29. flash memory characteristics symbol parameter conditions min (1) typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a ?40 to +105 c 40 52.5 70 s t erase page (1 kb) erase time t a ?40 to +105 c 20 40 ms t me mass erase time t a ?40 to +105 c 20 40 ms i dd supply current read mode f hclk = 72 mhz with 2 wait states, v dd = 3.3 v 20 ma write / erase modes f hclk = 72 mhz, v dd = 3.3 v 5m a power-down mode / halt, v dd = 3.0 to 3.6 v 50 a v prog programming voltage 2 3.6 v symbol parameter conditions value unit min (1) 1. based on characterization , not tested in production. typ max n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over t he whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 51/95 functional ems (electromagnetic susceptibility) while a simple application is executed on the device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure occurs. the failure is indicated by the leds: electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a functional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in ta b l e 3 1 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in relation with the emc level requested for his application. software recommendations the software flowchart must include the management of runaway conditions such as: corrupted program counter unexpected reset critical data corruption (control registers...) prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). table 31. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd 3.3 v, lqfp100, t a = +25 c, f hclk = 75 mhz, conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd 3.3 v, lqfp100, t a = +25 c, f hclk = 75 mhz, conforms to iec 61000-4-2 4a
electrical characteristics stm32f105xx, stm32f107xx 52/95 doc id 15274 rev 4 electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds thro ugh the i/o ports). this emissi on test is compliant with sae iec61967-2 standard which specifies the test board and the pin loading. 5.3.11 absolute maximum rati ngs (electrical sensitivity) based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determine its perfor mance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. static latch-up two complementary static tests are required on six parts to assess the latch-up performance: a supply overvoltage is applied to each power supply pin a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. table 32. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/48 mhz 8/72 mhz s emi peak level v dd 3.3 v, t a 25 c, lqfp100 package compliant with iec61967-2 0.1 to 30 mhz 9 9 dbv 30 to 130 mhz 26 13 130 mhz to 1ghz 25 31 sae emi level 4 4 - table 33. esd absolute maximum ratings symbol ratings conditions class maximum value (1) unit v esd(hbm) electrostatic discharge voltage (human body model) t a +25 c conforming to jesd22-a114 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a +25 c conforming to jesd22-c101 ii 500 1. based on characterization results, not tested in production. table 34. electrical sensitivities symbol parameter conditions class lu static latch-up class t a +105 c conforming to jesd78a ii level a
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 53/95 5.3.12 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in ta bl e 3 5 are derived from tests performed under the conditions summarized in ta b l e 9 . all i/os are cmos and ttl compliant. all i/os are cmos and ttl compliant (no software configuration required), their characteristics consider the most strict cmos-technology or ttl parameters: for v ih : ?i f v dd is in the [2.00 v - 3.08 v] range: cmos characteristics but ttl included ?i f v dd is in the [3.08 v - 3.60 v] range: ttl characteristics but cmos included for v il : ?i f v dd is in the [2.00 v - 2.28 v] range: ttl characteristics but cmos included ?i f v dd is in the [2.28 v - 3.60 v] range: cmos characteristics but ttl included table 35. i/o static characteristics symbol parameter conditions min typ max unit v il input low level voltage ttl ports ?0.5 0.8 v v ih standard io input high level voltage 2 v dd +0.5 io ft (1) input high level voltage 2 5.5v v il input low level voltage cmos ports ?0.5 0.35 v dd v v ih input high level voltage 0.65 v dd v dd +0.5 v hys standard io schmitt trigger voltage hysteresis (2) 200 mv io ft schmitt trigger voltage hysteresis (2) 5% v dd (3) mv i lkg input leakage current (4) v ss d v in d v dd standard i/os r 1 a v in = 5 v, i/o ft 3 r pu weak pull-up equivalent resistor (5) all pins except for pa 1 0 v in v ss 30 40 50 k : pa 1 0 8 1 1 1 5 r pd weak pull-down equivalent resistor (5) all pins except for pa 1 0 v in v dd 30 40 50 k : pa 1 0 8 1 1 1 5 c io i/o pin capacitance 5 pf 1. ft = five-volt tolerant. 2. hysteresis voltage between schmitt trigger switching levels. based on characteriza tion, not tested in production. 3. with a minimum of 100 mv. 4. leakage could be higher than max. if negativ e current is injected on adjacent pins. 5. pull-up and pull-down resistor s are designed with a true resistance in seri es with a switchable pmos/nmos. this mos/nmos contribution to the series resistance is minimum (~10% order) .
electrical characteristics stm32f105xx, stm32f107xx 54/95 doc id 15274 rev 4 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink +20 ma (with a relaxed v ol ). in the user application, the number of i/o pins which can drive current must be limited to respect the absolute maxi mum rating specified in section 5.2 : the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see ta bl e 7 ). the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see ta b l e 7 ). output voltage levels unless otherwise specified, the parameters given in ta bl e 3 6 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in ta bl e 9 . all i/os are cmos and ttl compliant. table 36. output voltage characteristics symbol parameter conditions min max unit v ol (1) 1. the i io current sunk by the device must always re spect the absolute maximu m rating specified in table 7 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin when 8 pins are sunk at same time ttl port i io = +8 ma 2.7 v < v dd < 3.6 v 0.4 v v oh (2) 2. the i io current sourced by the device must always re spect the absolute maximum rating specified in table 7 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4 v ol (1) output low level voltage for an i/o pin when 8 pins are sunk at same time cmos port i io =+ 8ma 2.7 v < v dd < 3.6 v 0.4 v v oh (2) output high level voltage for an i/o pin when 8 pins are sourced at same time 2.4 v ol (1)(3) 3. based on characterization data, not tested in production. output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +20 ma 2.7 v < v dd < 3.6 v 1.3 v v oh (2)(3) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?1.3 v ol (1)(3) output low level voltage for an i/o pin when 8 pins are sunk at same time i io = +6 ma 2 v < v dd < 2.7 v 0.4 v v oh (2)(3) output high level voltage for an i/o pin when 8 pins are sourced at same time v dd ?0.4
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 55/95 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 17 and ta bl e 3 7 , respectively. unless otherwise specified, the parameters given in ta bl e 3 7 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . table 37. i/o ac characteristics (1) 1. the i/o speed is configured using the modex[1:0] bi ts. refer to the stm32f10xxx reference manual for a description of gpio port configuration register. modex[1:0] bit value (1) symbol parameter conditions min max unit 10 f max(io)out maximum frequency (2) 2. the maximum frequency is defined in figure 17 . c l = 50 pf, v dd = 2 v to 3.6 v 2 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 125 (3) 3. guaranteed by design, not tested in production. ns t r(io)out output low to high level rise time 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v 10 mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v 25 (3) ns t r(io)out output low to high level rise time 25 (3) 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v 50 mhz c l = 50 pf, v dd = 2.7 v to 3.6 v 30 mhz c l = 50 pf, v dd = 2 v to 2.7 v 20 mhz t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v 12 (3) -t extipw pulse width of external signals detected by the exti controller 10 ns
electrical characteristics stm32f105xx, stm32f107xx 56/95 doc id 15274 rev 4 figure 17. i/o ac characteristics definition 5.3.13 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see ta bl e 3 5 ). unless otherwise specified, the parameters given in ta bl e 3 8 are derived from tests performed under the ambient temperature and v dd supply voltage conditions summarized in ta b l e 9 . ai14131 10% 90% 50% t r(io)out output ext ernal on 50pf maximum frequency is achieved if (t r + t f ) d 2/3)t and if the duty cycle is (45-55%) 10 % 50% 90% when loaded by 50pf t t r(io)out table 38. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) 1. guaranteed by design, not tested in production. nrst input low level voltage ?0.5 0.8 v v ih(nrst) (1) nrst input high level voltage 2 v dd +0.5 v hys(nrst) nrst schmitt trigger voltage hysteresis 200 mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in seri es with a switchable pmos . this pmos contribution to the series resistance must be minimum (~10% order) . v in v ss 30 40 50 k : v f(nrst) (1) nrst input filtered pulse 100 ns v nf(nrst) (1) nrst input not filtered pulse v dd > 2.7 v 300 ns
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 57/95 figure 18. recommended nrst pin protection 2. the reset network protects t he device against par asitic resets. 3. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 38 . otherwise the reset will not be taken into account by the device. 5.3.14 tim time r characteristics the parameters given in ta bl e 3 9 are guaranteed by design. refer to section 5.3.12: i/o port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, pwm output). a i141 3 2c s tm 3 2f10xxx r pu nr s t (2) v dd filter intern a l re s et 0.1 f extern a l re s et circ u it (1) table 39. timx (1) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3, tim4 and tim5 timers. symbol parameter conditions min max unit t res(tim) timer resolution time 1 t timxclk f timxclk = 72 mhz 13.9 ns f ext timer external clock frequency on ch1 to ch4 0 f timxclk /2 mhz f timxclk = 72 mhz 03 6m h z res tim timer resolution 16 bit t counter 16-bit counter clock period when internal clock is selected 1 65536 t timxclk f timxclk = 72 mhz 0.0139 910 s t max_count maximum possible count 65536 65536 t timxclk f timxclk = 72 mhz 59.6 s
electrical characteristics stm32f105xx, stm32f107xx 58/95 doc id 15274 rev 4 5.3.15 communications interfaces i 2 c interface characteristics unless otherwise specified, the parameters given in ta bl e 4 0 are derived from tests performed under the ambient temperature, f pclk1 frequency and v dd supply voltage conditions summarized in ta bl e 9 . the stm32f105xx and stm32f107xx i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in ta b l e 4 0 . refer also to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (sda and scl) . table 40. i 2 c characteristics symbol parameter standard mode i 2 c (1) 1. guaranteed by design, not tested in production. fast mode i 2 c (1)(2) 2. f pclk1 must be higher than 2 mhz to achieve the maximum standard mode i 2 c frequency. it must be higher than 4 mhz to achieve the maximum fast mode i 2 c frequency. unit min max min max t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0 (3) 3. the maximum hold time of the start condition has only to be met if the interface does not stretch the low period of scl signal. 0 (4) 4. the device must internally provide a hold time of at least 300ns for th e sda signal in order to bridge the undefined region of the falling edge of scl. 900 (3) t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b 300 t f(sda) t f(scl) sda and scl fall time 300 300 t h(sta) start condition hold time 4.0 0.6 s t su(sta) repeated start condition setup time 4.7 0.6 t su(sto) stop condition setup time 4.0 0.6 p s t w(sto:sta) stop to start condition time (bus free) 4.7 1.3 p s c b capacitive load for each bus line 400 400 pf
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 59/95 figure 19. i 2 c bus ac waveforms and measurement circuit 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . table 41. scl frequency (f pclk1 = 36 mhz.,v dd = 3.3 v) (1)(2) 1. r p = external pull-up resistance, f scl = i 2 c speed, 2. for speeds around 200 khz, the tole rance on the achieved speed is of r 5%. for other speed ranges, the tolerance on the achieved speed r 2%. these variations depend on the accuracy of the external components used to design the application. f scl (khz) i2c_ccr value r p = 4.7 k : 400 0x801e 300 0x8028 200 0x803c 100 0x00b4 50 0x0168 20 0x0384 ai14133c start sd a 100 4.7k i2c bus 4.7k 100 v dd v dd stm32f10xxx sda scl t f(sda) t r(sda) scl t h(sta) t w(sckh) t w(sckl) t su(sda) t r(sck) t f(sck) t h(sda) s tart repeated start t su(sta) t su(sto) s top t su(sta:sto)
electrical characteristics stm32f105xx, stm32f107xx 60/95 doc id 15274 rev 4 i 2 s - spi interface characteristics unless otherwise specified, the parameters given in ta bl e 4 2 for spi or in ta bl e 4 3 for i 2 s are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in ta bl e 9 . refer to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 42. spi characteristics (1) 1. remapped spi1 characteristics to be determined. symbol parameter conditions min max unit f sck 1/t c(sck) spi clock frequency master mode 18 mhz slave mode 18 t r(sck) t f(sck) spi clock rise and fall time capacitive load: c = 30 pf 8 ns ducy(sck) spi slave input clock duty cycle slave mode 30 70 % t su(nss) (2) 2. based on characterization , not tested in production. nss setup time slave mode 4 t pclk ns t h(nss) (2) nss hold time slave mode 2 t pclk t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f pclk = 36 mhz, presc = 4 50 60 t su(mi) (2) t su(si) (2) data input setup time master mode 5 slave mode 5 t h(mi) (2) t h(si) (2) data input hold time master mode 5 slave mode 4 t a(so) (2)(3) 3. min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. data output access time slave mode, f pclk = 20 mhz 0 3 t pclk t dis(so) (2)(4) 4. min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in hi-z data output disable time slave mode 2 10 t v(so) (2)(1) data output valid time slave mode (after enable edge) 25 t v(mo) (2)(1) data output valid time master mode (after enable edge) 5 t h(so) (2) data output hold time slave mode (after enable edge) 15 t h(mo) (2) master mode (after enable edge) 2
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 61/95 figure 20. spi timing diagram - slave mode and cpha = 0 figure 21. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cpha= 0 mosi input miso out p ut cpha= 0 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in nss input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cpha=1 mosi input miso out p ut cpha=1 ms b o u t msb in bi t6 ou t lsb in lsb out cpol=0 cpol=1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input
electrical characteristics stm32f105xx, stm32f107xx 62/95 doc id 15274 rev 4 figure 22. spi timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cpha= 0 mosi outut miso inp ut cpha= 0 ms bin m sb out bi t6 in lsb out lsb in cpol=0 cpol=1 b i t1 out nss input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cpha=1 cpha=1 cpol=0 cpol=1 t su(mi) t v(mo) t h(mo)
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 63/95 table 43. i 2 s characteristics (1) 1. tbd = to be determined. symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master tbd tbd mhz slave 0 tbd t r(ck) t f(ck) i 2 s clock rise and fall time capacitive load c l = 50 pf tbd ns t v(ws) (2) 2. based on design simulation and/or characte rization results, not tested in production. ws valid time master tbd t h(ws) (2) ws hold time master tbd t su(ws) (2) ws setup time slave tbd t h(ws) (2) ws hold time slave tbd t w(ckh) (2) t w(ckl) (2) ck high and low time master f pclk = tbd, presc = tbd tbd t su(sd_mr) (2) t su(sd_sr) (2) data input setup time master receiver slave receiver tbd tbd t h(sd_mr) (2)(3) t h(sd_sr) (2)(3) 3. depends on f pclk . for example, if f pclk =8 mhz, then t pclk = 1/f plclk =125 ns. data input hold time master receiver slave receiver tbd tbd t h(sd_mr) (2) t h(sd_sr) (2) data input hold time master f pclk = tbd slave f pclk = tbd tbd tbd t v(sd_st) (2)(3) data output valid time slave transmitter (after enable edge) tbd f pclk = tbd tbd t h(sd_st) (2) data output hold time slave transmitter (after enable edge) tbd t v(sd_mt) (2)(3) data output valid time master transmitter (after enable edge) tbd f pclk = tbd tbd tbd t h(sd_mt) (2) data output hold time master transmitter (after enable edge) tbd
electrical characteristics stm32f105xx, stm32f107xx 64/95 doc id 15274 rev 4 figure 23. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmit/receive is sent before the first byte. figure 24. i 2 s master timing diagram (philips protocol) (1) 1. based on characterization , not tested in production. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmit/receive is sent before the first byte. ck inp u t cpol = 0 cpol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t cpol = 0 cpol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2)
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 65/95 usb otg fs characteristics the usb otg interface is usb- if certified (full-speed). figure 25. usb otg fs timings: definiti on of data signal rise and fall time table 44. usb otg fs startup time symbol parameter max unit t startup (1) 1. guaranteed by design, not tested in production. usb otg fs transceiver startup time 1 s table 45. usb otg fs dc electrical characteristics symbol parameter conditions min. (1) 1. all the voltages are measured from the local ground potential. typ. max. (1) unit input levels v dd usb otg fs operating voltage 3.0 (2) 2. the stm32f105xx and stm32f107xx usb otg fs functi onality is ensured down to 2.7 v but not the full usb otg fs electrical c haracteristics which are degraded in the 2.7-to-3.0 v v dd voltage range. 3.6 v v di (3) 3. guaranteed by design, not tested in production. differential input sensitivity i(usbdp, usbdm) 0.2 v v cm (3) differential common mode range includes v di range 0.8 2.5 v se (3) single ended receiver threshold 1.3 2.0 output levels v ol static output level low r l of 1.5 k : to 3.6 v (4) 4. r l is the load connected on the usb otg fs drivers 0.3 v v oh static output level high r l of 15 k : to v ss (4) 2.8 3.6 r pd pull-down resistance on pa11, pa12 v in = v dd 17 21 24 k : pull-down resistance on pa 9 0.65 1.1 2.0 r pu pull-up resistance on pa12 v in = v ss 1.5 1.8 2.1 pull-up resistance on pa9 v in = v ss 0.25 0.37 0.55 ai14137 t f differen tial data lines v ss v cr s t r crossover points
electrical characteristics stm32f105xx, stm32f107xx 66/95 doc id 15274 rev 4 ethernet characteristics ta bl e 4 7 showns the ethernet operating voltage. ta bl e 4 8 gives the list of ethernet mac signals for the smi (station management interface) and figure 26 shows the corresponding timing diagram. figure 26. ethernet smi timing diagram table 46. usb otg fs electrical characteristics (1) 1. guaranteed by design, not tested in production. driver characteristics symbol parameter conditions min max unit t r rise time (2) 2. measured from 10% to 90% of the data signal. for more detailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 42 0n s t f fall time (2) c l = 50 pf 4 20 ns t rfm rise/ fall time matching t r /t f 90 110 % v crs output signal crossover voltage 1.3 2.0 v table 47. ethernet dc electrical characteristics symbol parameter min. (1) 1. all the voltages are measured from the local ground potential. max. (1) unit input level v dd ethernet operating voltage 3.0 3.6 v table 48. dynamics characteristics: ethernet mac signals for smi (1) 1. tbd stands for to be determined. symbol rating min typ max unit t mdc mdc cycle time (1.71 mhz, ahb = 72 mhz) 582.8 583.3 584 ns t d(mdio) mdio write data valid time 305.2 305.9 306.5 ns t su(mdio) read data setup time tbd tbd tbd ns t h(mdio) read data hold time tbd tbd tbd ns eth_mdceth_mdio(o) eth_mdio(i) t mdc t d(mdio) t su (mdio) t h(mdio) a i15666c
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 67/95 ta bl e 4 9 gives the list of ethernet mac signals for the rmii and figure 27 shows the corresponding timing diagram. figure 27. ethernet rmii timing diagram ta bl e 5 0 gives the list of ethernet mac signals for mii and figure 27 shows the corresponding timing diagram. figure 28. ethernet mii timing diagram table 49. dynamics characteristics: ethernet mac signals for rmii (1) 1. tbd stands for to be determined. symbol rating min typ max unit t su(rxd) receive data setup time tbd tbd tbd ns t ih(rxd) receive data hold time tbd tbd tbd ns t su(crs) carrier sense set-up time tbd tbd tbd ns t ih(crs) carrier sense hold time tbd tbd tbd ns t d(txen) transmit enable valid delay time 0 9.6 21.9 ns t d(txd) transmit data valid delay time 0 9.9 21 ns rmii_ref_clkrmii_tx_en rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv t d(txen) t d(txd) t su(rxd) t su(crs) t ih(rxd) t ih(crs) ai15667 mii_rx_clkmii_rxd[3:0] mii_rx_dv mii_rx_er t d(txen) t d(txd) t su(rxd) t su(er) t su(dv) t ih(rxd) t ih(er) t ih(dv) ai15668 mii_tx_clkmii_tx_en mii_txd[3:0]
electrical characteristics stm32f105xx, stm32f107xx 68/95 doc id 15274 rev 4 can (controller area network) interface refer to section 5.3.12: i/o port characteristics for more details on the input/output alternate function characteristics (cantx and canrx). 5.3.16 12-bit adc characteristics unless otherwise specified, the parameters given in ta bl e 5 1 are derived from tests performed under the ambient temperature, f pclk2 frequency and v dda supply voltage conditions summarized in ta bl e 9 . note: it is recommended to perform a calibration after each power-up. table 50. dynamics characteristics: ethernet mac signals for mii (1) 1. tbd stands for to be determined. symbol rating min typ max unit t su(rxd) receive data setup time tbd tbd tbd ns t ih(rxd) receive data hold time tbd tbd tbd ns t su(dv) data valid setup time tbd tbd tbd ns t ih(dv) data valid hold time tbd tbd tbd ns t su(er) error setup time tbd tbd tbd ns t ih(er) error hold time tbd tbd tbd ns t d(txen) transmit enable valid delay time 13.4 15.5 17.7 ns t d(txd) transmit data valid delay time 12.9 16.1 19.4 ns table 51. adc characteristics symbol parameter conditions min typ max unit v dda power supply 2.4 3.6 v v ref+ positive reference voltage 2.4 v dda v i vref current on the v ref input pin 160 (1) 220 (1) a f adc adc clock frequency 0.6 14 mhz f s (2) sampling rate 0.05 1 mhz f trig (2) external trigger frequency f adc = 14 mhz 823 khz 17 1/f adc v ain conversion voltage range (3) 0 (v ssa or v ref- tied to ground) v ref+ v r ain (2) external input impedance see equation 1 and ta bl e 5 2 for details 50 k : r adc (2) sampling switch resistance 1 k : c adc (2) internal sample and hold capacitor 8 pf t cal (2) calibration time f adc = 14 mhz 5.9 s 83 1/f adc
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 69/95 equation 1: r ain max formula the formula above ( equation 1 ) is used to determine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). t lat (2) injection trigger conversion latency f adc = 14 mhz 0.214 s 3 (4) 1/f adc t latr (2) regular trigger conversion latency f adc = 14 mhz 0.143 s 2 (4) 1/f adc t s (2) sampling time f adc = 14 mhz 0.107 17.1 s 1.5 239.5 1/f adc t stab (2) power-up time 0 0 1 s t conv (2) total conversion time (including sampling time) f adc = 14 mhz 1 18 s 14 to 252 (t s for sampling +12.5 for successive approximation) 1/f adc 1. based on characterization, not tested in production. 2. guaranteed by design, not tested in production. 3. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 4. for external triggers, a delay of 1/f pclk2 must be added to the latency specified in table 51 . table 51. adc characteristics (continued) symbol parameter conditions min typ max unit table 52. r ain max for f adc = 14 mhz (1) 1. based on characterization , not tested in production. t s (cycles) t s (s) r ain max (k : ) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 na 239.5 17.1 na r ain t s f adc c adc 2 n2 + ln u u ------------------------------------------------------------- - r adc ?
electrical characteristics stm32f105xx, stm32f107xx 70/95 doc id 15274 rev 4 note: adc accuracy vs. negative injection current: injecting a negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to standard analog pins which may potentially inject negative currents. any positive injectio n current within the limits specified for i inj(pin) and 6 i inj(pin) in section 5.3.12 does not affect the adc accuracy. table 53. adc accuracy - limited test conditions (1) 1. adc dc accuracy values are m easured after internal calibration. symbol parameter test conditions typ max (2) 2. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k : , v dda = 3 v to 3.6 v t a = 25 c measurements made after adc calibration 1.3 2 lsb eo offset error 1 1.5 eg gain error 0.5 1.5 ed differential linearity error 0.7 1 el integral linearity error 0.8 1.5 table 54. adc accuracy (1) (2) 1. adc dc accuracy values are m easured after internal calibration. 2. better performance could be achieved in restricted v dd , frequency and temperature ranges. symbol parameter test conditions typ max (3) 3. based on characterization , not tested in production. unit et total unadjusted error f pclk2 = 56 mhz, f adc = 14 mhz, r ain < 10 k : , v dda = 2.4 v to 3.6 v measurements made after adc calibration 2 5 lsb eo offset error 1.5 2.5 eg gain error 1.5 3 ed differential linearity error 1 2 el integral linearity error 1.5 3
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 71/95 figure 29. adc accura cy characteristics figure 30. typical connection diagram using the adc 1. refer to ta b l e 5 1 for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 40954094 4093 54 3 2 1 0 76 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = ai14139d stm32f10xxx v dd ainx i l 1 a 0.6 v v t r ain (1) c parasitic v ain 0.6 v v t r adc (1) c adc (1) 12-bit converter sample and hold adc converter
electrical characteristics stm32f105xx, stm32f107xx 72/95 doc id 15274 rev 4 general pcb design guidelines power supply decoupling should be performed as shown in figure 31 or figure 32 , depending on whether v ref+ is connected to v dda or not. the 10 nf capacitors should be ceramic (good quality). they should be placed them as close as possible to the chip. figure 31. power supply and reference decoupling (v ref+ not connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. figure 32. power supply and reference decoupling (v ref+ connected to v dda ) 1. v ref+ and v ref? inputs are available only on 100-pin packages. v ref+ stm32f10xxx v dda v ssa /v ref- 1 f // 10 nf 1 f // 10 nf ai14380 c (see note 1) (see note 1) v ref+ /v dda stm32f10xxx 1 f // 10 nf v ref? /v ssa ai14381 c (see note 1) (see note 1)
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 73/95 5.3.17 dac elect rical specifications table 55. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage 2.4 3.6 v v ref+ reference supply voltage 2.4 3.6 v v ref+ must always be below v dda v ssa ground 0 0 v r load (1) resistive load with buffer on 5 k : r o (1) impedance output with buffer off 15 k : when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m : c load (1) capacitive load 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v ref+ = 3.6 v and (0x155) to (0xeab) at v ref+ = 2.4 v dac_out max (1) higher dac_out voltage with buffer on v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off 0.5 mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off v ref+ ? 1lsb v i ddvref+ dac dc current consumption in quiescent mode (standby mode) 220 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs i dda dac dc current consumption in quiescent mode (standby mode) 380 a with no load, middle code (0x800) on the inputs 480 a with no load, worst code (0xf1c) at v ref+ = 3.6 v in terms of dc consumption on the inputs dnl (2) differential non linearity difference between two consecutive code-1lsb) 0.5 lsb given for the dac in 10-bit configuration. 2 lsb given for the dac in 12-bit configuration. inl (2) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) 1 lsb given for the dac in 10-bit configuration. 4 lsb given for the dac in 12-bit configuration.
electrical characteristics stm32f105xx, stm32f107xx 74/95 doc id 15274 rev 4 figure 33. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. offset (2) offset error (difference between measured value at code (0x800) and the ideal value = v ref+ /2) 10 mv given for the dac in 12-bit configuration 3 lsb given for the dac in 10-bit at v ref+ = 3.6 v 12 lsb given for the dac in 12-bit at v ref+ = 3.6 v gain error (2) gain error 0.5 % given for the dac in 12bit configuration t settling (2) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb 34 s c load d 50 pf, r load t 5 k : update rate (2) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) 1m s / s c load d 50 pf, r load t 5 k : t wakeup (2) wakeup time from off state (setting the enx bit in the dac control register) 6.5 10 s c load d 50 pf, r load t 5 k : input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement ?67 ?40 db no r load , c load = 50 pf 1. guaranteed by design, not tested in production. 2. guaranteed by characterizati on, not tested in production. table 55. dac characteristics (continued) symbol parameter min typ max unit comments r load c load b u ffered/non- bu ffered dac dacx_out b u ffer(1) 12- b it digit a l to a n a log converter a i17157
stm32f105xx, stm32f107xx electrical characteristics doc id 15274 rev 4 75/95 5.3.18 temperature sen sor characteristics table 56. ts characteristics symbol parameter min typ max unit t l (1) 1. based on characterization , not tested in production. v sense linearity with temperature r 1 r 2 c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 (1) voltage at 25 c 1.34 1.43 1.52 v t start (2) 2. guaranteed by design, not tested in production. startup time 4 10 s t s_temp (3)(2) 3. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 17.1 s
package characteristics stm32f105xx, stm32f107xx 76/95 doc id 15274 rev 4 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stm32f105xx, stm32f107xx package characteristics doc id 15274 rev 4 77/95 figure 34. lqfp100, 100-pin low-profile quad flat package outline (1) figure 35. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. dd1 d3 75 51 50 76 100 26 12 5 e3 e1 e e b pin 1identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 table 57. lqpf100 ? 100-pin low-profile quad flat package mechanical data symbol millimeters inches (1) typ min max typ min max a 1.60 0.063 a1 0.05 0.15 0.002 0.0059 a2 1.40 1.35 1.45 0.0551 0.0531 0.0571 b 0.22 0.17 0.27 0.0087 0.0067 0.0106 c 0.09 0.20 0.0035 0.0079 d 16.00 15.80 16.20 0.6299 0.622 0.6378 d1 14.00 13.80 14.20 0.5512 0.5433 0.5591 d3 12.00 0.4724 e 16.00 15.80 16.20 0.6299 0.622 0.6378 e1 14.00 13.80 14.20 0.5512 0.5433 0.5591 e3 12.00 0.4724 e0 . 5 0 0 . 0 1 9 7 l 0.60 0.45 0.75 0.0236 0.0177 0.0295 l1 1.00 0.0394 k3 . 5 0 7 3 . 5 0 7 ccc 0.08 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
package characteristics stm32f105xx, stm32f107xx 78/95 doc id 15274 rev 4 figure 36. lqfp64 ? 64 pin low-profile quad flat package outline (1) figure 37. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. a a2 a1 c l1 e e1 d d1 e b a i14 3 9 8b l 48 32 49 64 17 11 6 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 table 58. lqfp64 ? 64 pin low-profile quad flat package mechanical data dim. mm inches (1) min typ max min typ max a 1.60 0.0630 a1 0.05 0.15 0.0020 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 d 12.00 0.4724 d1 10.00 0.3937 e 12.00 0.4724 e1 10.00 0.3937 e 0.50 0.0197 t 0 3.5 7 0 3.5 7 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0394 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f105xx, stm32f107xx package characteristics doc id 15274 rev 4 79/95 6.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 9: general operating conditions on page 34 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max 4 ja ) where: t a max is the maximum ambient temperature in q c, 4 ja is the package junction-to-ambient thermal resistance, in q c/w, p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = 6 (v ol i ol ) + 6 ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 6.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). ava ilable from www.jedec.org. table 59. package thermal characteristics symbol parameter value unit 4 ja thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 46 c/w thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45
package characteristics stm32f105xx, stm32f107xx 80/95 doc id 15274 rev 4 6.2.2 selecting the pro duct temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 60: ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. as applications do not commonly use the stm32f 103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. the following examples show how to calculate the temperature range needed for a given application. example 1: high-performance application assuming the following application conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw: p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in ta b l e 5 9 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 82 c + (46 c/w 447 mw) = 82 c + 20.6 c = 102.6 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at least with the temperature range suffix 6 (see table 60: ordering information scheme ). example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following application conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 20 8 ma 0.4 v = 64 mw this gives: p intmax = 70 mw and p iomax = 64 mw: p dmax = 70 + 64 = 134 mw thus: p dmax = 134 mw
stm32f105xx, stm32f107xx package characteristics doc id 15274 rev 4 81/95 using the values obtained in ta b l e 5 9 t jmax is calculated as follows: ? for lqfp100, 46 c/w t jmax = 115 c + (46 c/w 134 mw) = 115 c + 6.2 c = 121.2 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at least with the temperature range suffix 7 (see table 60: ordering information scheme ). figure 38. lqfp100 p d max vs. t a 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 t a (c) p d (mw) suffix 6 suffix 7
part numbering stm32f105xx, stm32f107xx 82/95 doc id 15274 rev 4 7 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 60. ordering information scheme example: stm32 f 105 r c t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 105 = connectivity, usb otg fs 107= connectivity, usb otg fs & ethernet pin count r = 64 pins v = 100 pins flash memory size 8 = 64 kbytes of flash memory b = 128 kbytes of flash memory c = 256 kbytes of flash memory package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c. 7 = industrial temperature range, ?40 to 105 c. options xxx = programmed parts tr = tape and real
stm32f105xx, stm32f107xx applicative block diagrams doc id 15274 rev 4 83/95 appendix a applicative block diagrams a.1 usb otg fs interface solutions figure 39. usb otg fs device mode 1. v dd ranges between 2 v and 3.6 v. 2. use a regulator if you want to build a bus-powered device. u s b otg f u ll- s peed core s tm 3 2f105xx/ s tm 3 2f107xx u s b f u ll- s peed tr a n s ceiver dp u s b micro-b connector dm v bu s v ss hnp hnp s rp s rp v dd (1) id id otg phy a i1565 3b dpdm v bu s v ss to ho s t 5 v to v dd reg u l a tor (2)
applicative block diagrams stm32f105xx, stm32f107xx 84/95 doc id 15274 rev 4 figure 40. host connection 1. stmps2141str needed only if the applicat ion has to support bus-powered devices. 2. v dd ranges between 2 v and 3.6 v. u s b otg f u ll- s peed core s tm 3 2f105xx/ s tm 3 2f107xx u s b f u ll- s peed/ low- s peed tr a n s ceiver dp u s b s td-a connector dm v bu s v ss hnp hnp s rp s rp id id otg phy a i15654 b gpio gpio + irq en ovrcrfl a g c u rrent-limited power di s tri bu tion s witch s tmp s 2141 s tr (1) v dd (2) 5 v
stm32f105xx, stm32f107xx applicative block diagrams doc id 15274 rev 4 85/95 figure 41. otg connection (any protocol) 1. stmps2141str needed only if the applicat ion has to support bus-powered devices. 2. v dd ranges between 2 v and 3.6 v. a.2 ethernet interface solutions figure 42. mii mode using a 25 mhz crystal 1. hclk must be greater than 25 mhz. 2. pulse per second when using ieee1588 ptp, optional signal. u s b otg f u ll- s peed core s tm 3 2f105xx/ s tm 3 2f107xx u s b f u ll- s peed/ low- s peed tr a n s ceiver dp u s b micro-ab connector dm v bu s v ss hnp hnp s rp s rp id id otg phy a i15655 b gpio gpio + irq en c u rrent-limited power di s tri bu tion s witch s tmp s 2141 s tr (1) id ovrcrfl a g v dd (2) 5 v mcu ethernetmac 10/100 ethernetphy 10/100 pll hclk xt1 phy_clk 25 mhz mii_rx_clkmii_rxd[3:0] mii_rx_dv mii_rx_er mii_tx_clkmii_tx_en mii_txd[3:0] mii_crs mii_col mdiomdc hclk (1) pps_out (2) xtal 25 mhz stm32f107xx osc tim2 timestamp comparator timer input trigger ieee1588 ptp mii = 15 pins mii + mdc = 17 pins ai15656
applicative block diagrams stm32f105xx, stm32f107xx 86/95 doc id 15274 rev 4 figure 43. rmii with a 50 mhz oscillator 1. hclk must be greater than 25 mhz. figure 44. rmii with a 25 mhz crystal and phy with pll 1. hclk must be greater than 25 mhz. mcu ethernetmac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 50 mhz rmii_rxd[1:0]rmii_crx_dv rmii_ref_clk rmii_tx_enrmii_txd[1:0] mdiomdc hclk (1) stm32f107xx osc 50 mhz tim2 timestamp comparator timer input trigger ieee1588 ptp rmii = 7 pins rmii + mdc = 9 pins ai15657 /2 or /20 synchronous 2.5 or 25 mhz 50 mhz 50 mhz mcu ethernetmac 10/100 ethernet phy 10/100 pll hclk xt1 phy_clk 25 mhz rmii_rxd[1:0]rmii_crx_dv rmii_ref_clk rmii_tx_enrmii_txd[1:0] mdiomdc hclk (1) stm32f107xx tim2 timestamp comparator timer input trigger ieee1588 ptp rmii = 7 pins rmii + mdc = 9 pins ai15658 /2 or /20 synchronous 2.5 or 25 mhz 50 mhz xtal 25 mhz osc pll ref_clk
stm32f105xx, stm32f107xx applicative block diagrams doc id 15274 rev 4 87/95 figure 45. rmii with a 25 mhz crystal 1. the ns dp83848 is recommended as the input jitter requirement of this phy. it is compliant with the output jitter specification of the mcu. mcu ethernetmac 10/100 ethernet phy 10/100 pll s xt1/xt2 rmii_rxd[1:0]rmii_crx_dv rmii_ref_clk rmii_tx_enrmii_txd[1:0] mdio mdc hclk s tm 3 2f107xx tim2 time s t a mp comp a r a tor timer inp u t trigger ieee15 88 ptp rmii = 7 pin s rmii + mdc = 9 pin s a i15659 b 50 mhz xtal 25 mhz o s c n s dp 838 4 8 (1) 50 mhz 50 mhz
applicative block diagrams stm32f105xx, stm32f107xx 88/95 doc id 15274 rev 4 a.3 complete audio player solutions two solutions are offe red, illustrated in figure 46 and figure 47 . figure 46 shows storage media to audio dac/amplifier streaming using a software codec. this solution implements an audio crystal to provide audio class i 2 s accuracy on the master clock (0.5% error maximum, see the serial peripheral interface section in the reference manual for details). figure 46. complete audio player solution 1 figure 47 shows storage media to audio codec/amplifier streaming with sof synchronization of input/output audio streaming using a hardware codec. figure 47. complete audio player solution 2 cortex-m3 core 72 mhz otg (host mode) + phy spi spi gpio i2s xtal 14.7456 mhz usb mass-storage device mmc/ sdcard lcd touch screen control buttons dac + audio ampli file system program memory audio codec user application stm32f105/stm32f107 ai15660 cortex-m3 core 72 mhz otg + phy spi spi gpio i2s xtal 14.7456 mhz usb mass-storage device mmc/ sdcard lcd touch screen control buttons audio ampli file system program memory audio codec user application stm32f105/stm32f107 ai15661 sof sof synchronization of input/output audio streaming
stm32f105xx, stm32f107xx applicative block diagrams doc id 15274 rev 4 89/95 a.4 usb otg fs interface + ethernet/i 2 s interface solutions with the clock tree implemented on the stm32f107xx, only one crystal is required to work with both the usb (host/device/otg) and the ethernet (mii/rmii) interfaces. figure 48 illustrate the solution. figure 48. usb otg fs + ethernet solution with the clock tree implemented on the stm32f107xx, only one crystal is required to work with both the usb (host/device/otg) and the i 2 s (audio) interfaces. figure 49 illustrate the solution. figure 49. usb otg fs + i 2 s (audio) solution 25 mhz xtal otg 4 8 mhz mco pll2 x 8 o s c o s c mcu mco div b y 5 s el div b y 3 pll x9 vco o u t x1 8 div b y 5 ethernet phy phy s tm 3 2f107 cortex-m 3 core up to 50 mhz i2 s pll 3 x10 s clk mclk 2 % a cc u r a cy error u p to 72 mhz a i15662 b s el 14.7456 mhz xtal otg 47.92 3 2 mhz mco pll2 x12 o s c o s c mcu mco div b y 4 s el div b y 3 pll x6.5 vco o u t x1 3 div b y 4 phy s tm 3 2f105/ s tm 3 2f107 cortex-m 3 core up to 147.456 mhz i2 s pll 3 vco o u t x40 s clk mclk le ss th a n 0.5 % a cc u r a cy error on mclk a nd s clk up to71. 88 mhz a i1566 3b 0.16 % a cc u r a cy error
applicative block diagrams stm32f105xx, stm32f107xx 90/95 doc id 15274 rev 4 ta bl e 6 2 give the i dd run mode values that correspond to the conditions specified in ta bl e 6 1 . table 61. pll configurations application crystal value in mhz (xt1) prediv2 pll2mul pllsrc prediv1 pllmul usb prescaler (pllvco output) pll3mul i2sn clock input mco (main clock output) ethernet only 25 /5 pll2on x8 pll2 /5 pllon x9 na pll3on x10 na xt1 (mii) pll3 (rmii) ethernet + otg 25 /5 pll2on x8 pll2 /5 pllon x9 /3 pll3on x10 na xt1 (mii) pll3 (rmii) ethernet + otg + basic audio 25 /5 pll2on x8 pll2 /5 pllon x9 /3 pll3on x10 pll xt1 (mii) pll3 (rmii) ethernet + otg + audio class i 2 s (1) 14.7456 /4 pll2on x12 pll2 /4 pllon x6.5 /3 pll3on x20 pll3 vco out na eth phy must use its own crystal otg only 8 na pll2off xt1 /1 pllon x9 /3 pll3off na na otg + basic audio 8 na pll2off xt1 /1 pllon x9 /3 pll3off pll na otg + audio class i 2 s (1) 14.7456 /4 pll2on x12 pll2 /4 pllon x6.5 /3 pll3on x20 pll3 vco out na audio class i 2 s only (1) 14.7456 /4 pll2on x12 pll2 /4 pllon x6.5 na pll3on x20 pll3 vco out na 1. sysclk is set to be at 72 mhz except in this case where sysclk is at 71.88 mhz.
stm32f105xx, stm32f107xx applicative block diagrams doc id 15274 rev 4 91/95 table 62. applicative current consumption in run mode, code with data processing running from flash symbol parameter conditions (1) 1. v dd = 3.3 v. typ (2) 2. based on characterization , not tested in production. max (2) unit 85 c 105 c i dd supply current in run mode external clock, all peripherals enabled except ethernet, hse = 8 mhz, f hclk = 72 mhz, no mco 57 63 64 ma external clock, all peripherals enabled except ethernet, hse = 14.74 mhz, f hclk = 72 mhz, no mco 60.5 67 68 external clock, all peripherals enabled except otg, hse = 25 mhz, f hclk = 72 mhz, mco = 25 mhz 53 60.7 61 external clock, all peripherals enabled, hse = 25 mhz, f hclk = 72 mhz, mco = 25 mhz 60.5 65.5 66 external clock, all peripherals enabled, hse = 25 mhz, f hclk = 72 mhz, mco = 50 mhz 64 69.7 70 external clock, all peripherals enabled, hse = 50 mhz (3) , f hclk = 72 mhz, no mco 3. external oscillator. 62.5 67.5 68 external clock, only otg enabled, hse = 8 mhz, f hclk = 48 mhz, no mco 26.7 none none external clock, only ethernet enabled, hse = 25 mhz, f hclk = 25 mhz, mco = 25 mhz 14.3 none none
revision history stm32f105xx, stm32f107xx 92/95 doc id 15274 rev 4 revision history table 63. document revision history date revision changes 18-dec-2008 1 initial release. 20-feb-2009 2 i/o information clarified on page 1 . figure 4: stm32f105xxx and stm32f107xxx connectivity line bga100 ballout top view corrected. section 2.3.8: boot modes updated. pb4, pb13, pb14, pb15, pb3/tr aceswo moved from default column to remap column, plus small additional changes in ta b l e 5 : pin definitions . consumption values modified in section 5.3.5: supply current characteristics . note modified in table 13: maximum current consumption in run mode, code with data processing running from flash and table 15: maximum current consumption in sleep mode, code running from flash or ram . table 20: high-speed external user clock characteristics and table 21: low-speed external user clock characteristics modified. table 27: pll characteristics modified and table 28: pll2 and pll3 characteristics added.
stm32f105xx, stm32f107xx revision history doc id 15274 rev 4 93/95 19-jun-2009 3 section 2.3.8: boot modes and section 2.3.20: ethernet mac interface with dedicated dma and ieee 1588 support updated. section 2.3.24: remap capability added. figure 1: stm32f105xx and stm32f107xx connectivity line block diagram and figure 4: memory map updated. in table 5: pin definitions : ? i2s3_ws, i2s3_ck and i2s3_sd default alternate functions added ? small changes in signal names ? note 5 modified ? eth_mii_pps_out and eth_rmii_pps_out replaced by eth_pps_out ? eth_mii_mdio and eth_rmii_m dio replaced by eth_mdio ? eth_mii_mdc and eth_rmii_mdc replaced by eth_mdc figures: typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals enabled and typical current consumption in run mode versus frequency (at 3.6 v) - code with data processing running from ram, peripherals disabled removed. table 13: maximum current consumption in run mode, code with data processing running from flash , table 14: maximum current consumption in run mode, code with data processing running from ram and table 15: maximum current consumption in sleep mode, code running from flash or ram are to be determined. figure 11 and figure 12 show typical curves. pll1 renamed to pll. i dd supply current in stop mode modified in table 16: typical and maximum current consumptions in stop and standby modes . figure 10: typical current consumption in stop mode with regulator in run mode versus tem perature at different v dd values , figure 12: typical current consumption in standby mode versus temperature at different v dd values and figure 12: typical current consumption in standby mode versus temperature at different v dd values updated. table 17: typical current consumption in run mode, code with data processing running from flash , table 18: typical current consumption in sleep mode, code running from flash or ram and table 19: peripheral current consumption updated. f hse_ext modified in table 20: high-speed external user clock characteristics . min pll input clock (f pll_in ), f pll_out min and f pll_vco min modified in table 27: pll characteristics . acc hsi max values modified in table 24: hsi oscillator characteristics . table 31: ems characteristics and ta b l e 3 2 : e m i characteristics updated. table 42: spi characteristics updated. modified: figure 23: i 2 s slave timing diagram (philips protocol) (1) , figure 24: i 2 s master timing diagram (philips protocol) (1) and figure 26: ethernet smi timing diagram . bga100 package removed. section 6.2: therma l characteristics added. small text changes. table 63. document revision history (continued) date revision changes
revision history stm32f105xx, stm32f107xx 94/95 doc id 15274 rev 4 14-sep-2009 4 document status promot ed from preliminary data to full datasheet. number of dacs corrected in table 3: stm32f105xx and stm32f107xx family versus stm32f103xx family . note 4 added in table 5: pin definitions . v rerint and t coeff added to table 12: embedded internal reference voltage . values added to table 13: maximum current consumption in run mode, code with data processing running from flash , ta b l e 1 4 : maximum current consumption in run mode, code with data processing running from ram and table 15: maximum current consumption in sleep mode, code running from flash or ram . typical i dd_vbat value added in ta b l e 1 6 : ty p i c a l a n d m a x i m u m current consumptions in stop and standby modes . figure 9: typical current consumption on v bat with rtc on vs. temperature at different v bat values added. values modified in table 17: typical current consumption in run mode, code with data processing running from flash and table 18: typical current consumption in sl eep mode, code running from flash or ram . f hse_ext min modified in table 20: high-speed external user clock characteristics . c l1 and c l2 replaced by c in table 22: hse 3-25 mhz oscillator characteristics and table 23: lse oscillator characteristics (f lse = 32.768 khz) , notes modified and moved below the tables. note 1 modified below figure 15: typical application with an 8 mhz crystal . conditions removed from table 26: low-power mode wakeup timings . standards modified in section 5.3.10: emc characteristics on page 50 , conditions modified in table 31: ems characteristics . jitter maximum values added to table 27: pll characteristics and table 28: pll2 and pll3 characteristics . r pu and r pd modified in table 35: i/o static characteristics . condition added for v nf(nrst) parameter in table 38: nrst pin characteristics . note removed and r pd , r pu values added in table 45: usb otg fs dc electrical characteristics . table 47: ethernet dc electrical characteristics added. parameter values added to table 48: dynamics characteristics: ethernet mac signals for smi , table 49: dynamics characteristics: ethernet mac signals for rmii and table 50: dynamics characteristics: ethernet mac signals for mii . c adc and r ain parameters modified in table 51: adc characteristics . r ain max values modified in ta bl e 5 2 : r ain max for f adc = 14 mhz . table 55: dac characteristics modified. figure 33: 12-bit buffered /non-buffered dac added. table 62: applicative current consumption in run mode, code with data processing running from flash added. small text changes. table 63. document revision history (continued) date revision changes
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